derek.holloway
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60 lines
2.9 KiB
LLVM
60 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios6.0.0"
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; Multiple insert elements from loads into d subregisters are expensive on swift
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; due to renaming constraints.
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%T_i8v = type <8 x i8>
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%T_i8 = type i8
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define void @insertelement_i8(ptr %saddr, ptr %vaddr) {
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; CHECK-LABEL: 'insertelement_i8'
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <8 x i8>, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %saddr, align 1
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; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <8 x i8> %v0, i8 %v1, i32 1
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; CHECK-NEXT: Cost Model: Found costs of 1 for: store <8 x i8> %v2, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
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;
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%v0 = load %T_i8v, ptr %vaddr
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%v1 = load %T_i8, ptr %saddr
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%v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 1
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store %T_i8v %v2, ptr %vaddr
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ret void
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}
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%T_i16v = type <4 x i16>
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%T_i16 = type i16
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define void @insertelement_i16(ptr %saddr, ptr %vaddr) {
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; CHECK-LABEL: 'insertelement_i16'
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <4 x i16>, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i16, ptr %saddr, align 2
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; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <4 x i16> %v0, i16 %v1, i32 1
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; CHECK-NEXT: Cost Model: Found costs of 1 for: store <4 x i16> %v2, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
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;
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%v0 = load %T_i16v, ptr %vaddr
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%v1 = load %T_i16, ptr %saddr
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%v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 1
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store %T_i16v %v2, ptr %vaddr
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ret void
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}
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%T_i32v = type <2 x i32>
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%T_i32 = type i32
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define void @insertelement_i32(ptr %saddr, ptr %vaddr) {
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; CHECK-LABEL: 'insertelement_i32'
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v0 = load <2 x i32>, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i32, ptr %saddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of 3 for: %v2 = insertelement <2 x i32> %v0, i32 %v1, i32 1
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; CHECK-NEXT: Cost Model: Found costs of 1 for: store <2 x i32> %v2, ptr %vaddr, align 4
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; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
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;
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%v0 = load %T_i32v, ptr %vaddr
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%v1 = load %T_i32, ptr %saddr
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%v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 1
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store %T_i32v %v2, ptr %vaddr
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ret void
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}
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