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65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; RUN: llc %s -o - -verify-machineinstrs -mtriple=aarch64 -mattr=+lse -O0 | FileCheck %s
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; RUN: llc %s -o - -verify-machineinstrs -mtriple=aarch64 -mattr=+lse -O1 | FileCheck %s
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; When their destination register is WZR/ZZR, SWP operations are not regarded as
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; a read for the purpose of a DMB.LD in the AArch64 memory model.
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; This test ensures that the AArch64DeadRegisterDefinitions pass does not
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; replace the desitnation register of SWP instructions with the zero register
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; when the read value is unused.
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define dso_local i32 @atomic_exchange_monotonic(ptr %ptr, ptr %ptr2, i32 %value) {
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; CHECK-LABEL: atomic_exchange_monotonic:
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; CHECK: // %bb.0:
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; CHECK-NEXT: swp
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; CHECK-NOT: wzr
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x1]
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; CHECK-NEXT: ret
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%r0 = atomicrmw xchg ptr %ptr, i32 %value monotonic
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fence acquire
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%r1 = load atomic i32, ptr %ptr2 monotonic, align 4
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ret i32 %r1
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}
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define dso_local i32 @atomic_exchange_acquire(ptr %ptr, ptr %ptr2, i32 %value) {
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; CHECK-LABEL: atomic_exchange_acquire:
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; CHECK: // %bb.0:
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; CHECK-NEXT: swpa
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; CHECK-NOT: wzr
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x1]
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; CHECK-NEXT: ret
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%r0 = atomicrmw xchg ptr %ptr, i32 %value acquire
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fence acquire
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%r1 = load atomic i32, ptr %ptr2 monotonic, align 4
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ret i32 %r1
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}
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define dso_local i32 @atomic_exchange_release(ptr %ptr, ptr %ptr2, i32 %value) {
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; CHECK-LABEL: atomic_exchange_release:
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; CHECK: // %bb.0:
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; CHECK-NEXT: swpl
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; CHECK-NOT: wzr
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x1]
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; CHECK-NEXT: ret
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%r0 = atomicrmw xchg ptr %ptr, i32 %value release
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fence acquire
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%r1 = load atomic i32, ptr %ptr2 monotonic, align 4
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ret i32 %r1
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}
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define dso_local i32 @atomic_exchange_acquire_release(ptr %ptr, ptr %ptr2, i32 %value) {
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; CHECK-LABEL: atomic_exchange_acquire_release:
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; CHECK: // %bb.0:
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; CHECK-NEXT: swpal
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; CHECK-NOT: wzr
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; CHECK-NEXT: dmb ishld
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; CHECK-NEXT: ldr w0, [x1]
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; CHECK-NEXT: ret
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%r0 = atomicrmw xchg ptr %ptr, i32 %value acq_rel
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fence acquire
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%r1 = load atomic i32, ptr %ptr2 monotonic, align 4
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ret i32 %r1
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}
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