derek.holloway
7502bf64a4
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282 lines
9.9 KiB
YAML
282 lines
9.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: srem_pos_pow2_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_pos_pow2_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C1]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: srem_neg_pow2_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_neg_pow2_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C1]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 -4
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: srem_one_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_one_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $w0 = COPY [[C]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: srem_minus_one_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_minus_one_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $w0 = COPY [[C]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 -1
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: srem_intmin_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_intmin_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C1]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 -2147483648
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: srem_pow2_s64
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: srem_pow2_s64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C1]](s64)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ASHR]], [[C]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $x0 = COPY [[SUB]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = G_CONSTANT i64 8
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%2:_(s64) = G_SREM %0, %1
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: srem_pow2_v4s32_splat
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: srem_pow2_v4s32_splat
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR1]](<4 x s32>)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[ASHR]], [[BUILD_VECTOR]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[ADD]], [[BUILD_VECTOR]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 4
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%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
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%3:_(<4 x s32>) = G_SREM %0, %2
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$q0 = COPY %3(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: srem_pow2_v4s32_mixed_sign
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: srem_pow2_v4s32_mixed_sign
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR1]](<4 x s32>)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[ASHR]], [[BUILD_VECTOR]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[COPY]], [[AND]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[ADD]], [[BUILD_VECTOR]]
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[AND1]], [[AND]]
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; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%c0:_(s32) = G_CONSTANT i32 4
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%c1:_(s32) = G_CONSTANT i32 -8
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%c2:_(s32) = G_CONSTANT i32 16
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%c3:_(s32) = G_CONSTANT i32 -1
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%1:_(<4 x s32>) = G_BUILD_VECTOR %c0, %c1, %c2, %c3
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%2:_(<4 x s32>) = G_SREM %0, %1
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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# Negative test: non-pow2 divisor should not match.
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name: srem_nonpow2_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_nonpow2_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655766
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; CHECK-NEXT: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SMULH]], [[C1]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SMULH]], [[LSHR]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -3
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ADD]], [[C2]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[MUL]]
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; CHECK-NEXT: $w0 = COPY [[ADD1]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 3
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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# Negative test: non-constant divisor should not match.
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name: srem_nonconst_s32
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: srem_nonconst_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SREM]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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# Negative test: zero divisor should not match.
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name: srem_zero_s32
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: srem_zero_s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[C]]
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; CHECK-NEXT: $w0 = COPY [[SREM]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = G_SREM %0, %1
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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