TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s

---
name:   sub_minus_one
body:             |
  bb.0:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: sub_minus_one
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(s64) = COPY $x0
    ; CHECK-NEXT: %c1:_(s64) = G_CONSTANT i64 -1
    ; CHECK-NEXT: %sub:_(s64) = G_XOR %a, %c1
    ; CHECK-NEXT: $x0 = COPY %sub(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %a:_(s64) = COPY $x0
    %c1:_(s64) = G_CONSTANT i64 -1
    %sub:_(s64) = G_SUB %c1, %a
    $x0 = COPY %sub
    RET_ReallyLR implicit $x0

...
---
name:   sub_minus_one_vector
body:             |
  bb.0:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: sub_minus_one_vector
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: %neg_one:_(s16) = G_CONSTANT i16 -1
    ; CHECK-NEXT: %c1:_(<4 x s16>) = G_BUILD_VECTOR %neg_one(s16), %neg_one(s16), %neg_one(s16), %neg_one(s16)
    ; CHECK-NEXT: %sub:_(<4 x s16>) = G_XOR %a, %c1
    ; CHECK-NEXT: $x0 = COPY %sub(<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %a:_(<4 x s16>) = COPY $x0
    %neg_one:_(s16) = G_CONSTANT i16 -1
    %c1:_(<4 x s16>) = G_BUILD_VECTOR %neg_one(s16), %neg_one(s16), %neg_one(s16), %neg_one(s16)
    %sub:_(<4 x s16>) = G_SUB %c1, %a
    $x0 = COPY %sub
    RET_ReallyLR implicit $x0

...
---
name: sub_one_from_sub
body:             |
  bb.1:
  liveins: $w0, $w1

    ; CHECK-LABEL: name: sub_one_from_sub
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C]]
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[XOR]], [[COPY]]
    ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %cst:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_SUB %2, %cst
    $w0 = COPY %3(s32)
...

---
name: sub_one_from_sub_vec
body:             |
  bb.1:
  liveins: $x0, $x1

    ; CHECK-LABEL: name: sub_one_from_sub_vec
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $x1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[COPY1]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[XOR]], [[COPY]]
    ; CHECK-NEXT: $x0 = COPY [[ADD]](<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %0:_(<4 x s16>) = COPY $x0
    %1:_(<4 x s16>) = COPY $x1
    %c1:_(s16) = G_CONSTANT i16 1
    %cst:_(<4 x s16>) = G_BUILD_VECTOR %c1(s16), %c1(s16), %c1(s16), %c1(s16)
    %2:_(<4 x s16>) = G_SUB %0, %1
    %3:_(<4 x s16>) = G_SUB %2, %cst
    $x0 = COPY %3
    RET_ReallyLR implicit $x0
...

---
name: sub_one_from_sub_one_use
body:             |
  bb.1:
  liveins: $w0, $w1

    ; CHECK-LABEL: name: sub_one_from_sub_one_use
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C]]
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[ADD]]
    ; CHECK-NEXT: $w0 = COPY [[MUL]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %cst:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_SUB %2, %cst
    %4:_(s32) = G_MUL %2, %3
    $w0 = COPY %4(s32)