derek.holloway
7502bf64a4
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223 lines
9.8 KiB
LLVM
223 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=aarch64-postlegalizer-combiner -force-legal-indexing %s -o - | FileCheck %s
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; RUN: llc -debugify-and-strip-all-safe -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=aarch64-postlegalizer-combiner -force-legal-indexing %s -o - | FileCheck %s
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define ptr @test_simple_load_pre(ptr %ptr) {
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; CHECK-LABEL: name: test_simple_load_pre
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 1 :: (volatile load (i8) from %ir.next)
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; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr i8, ptr %ptr, i32 42
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load volatile i8, ptr %next
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ret ptr %next
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}
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define ptr @test_unused_load_pre(ptr %ptr) {
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; CHECK-LABEL: name: test_unused_load_pre
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
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; CHECK-NEXT: $x0 = COPY [[C1]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr i8, ptr %ptr, i32 42
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load volatile i8, ptr %next
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ret ptr null
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}
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define ptr @test_simple_store_pre(ptr %ptr) {
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; CHECK-LABEL: name: test_simple_store_pre
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
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; CHECK-NEXT: [[INDEXED_STORE:%[0-9]+]]:_(p0) = G_INDEXED_STORE [[C1]](i8), [[COPY]], [[C]](i64), 1 :: (volatile store (i8) into %ir.next)
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; CHECK-NEXT: $x0 = COPY [[INDEXED_STORE]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr i8, ptr %ptr, i32 42
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store volatile i8 0, ptr %next
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ret ptr %next
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}
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; The potentially pre-indexed address is used as the value stored. Converting
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; would produce the value too late but only by one instruction.
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define ptr @test_store_pre_val_loop(ptr %ptr) {
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; CHECK-LABEL: name: test_store_pre_val_loop
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 336
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
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; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[PTR_ADD]](p0) :: (volatile store (p0) into %ir.next)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr ptr, ptr %ptr, i32 42
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store volatile ptr %next, ptr %next
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ret ptr %next
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}
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; Potentially pre-indexed address is used between GEP computing it and load.
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define ptr @test_load_pre_before(ptr %ptr) {
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; CHECK-LABEL: name: test_load_pre_before
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: BL @bar, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr i8, ptr %ptr, i32 42
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call void @bar(ptr %next)
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load volatile i8, ptr %next
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ret ptr %next
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}
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; Materializing the base into a writable register (from sp/fp) would be just as
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; bad as the original GEP.
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define ptr @test_alloca_load_pre() {
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; CHECK-LABEL: name: test_alloca_load_pre
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile dereferenceable load (i8) from %ir.next)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%ptr = alloca i8, i32 128
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%next = getelementptr i8, ptr %ptr, i32 42
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load volatile i8, ptr %next
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ret ptr %next
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}
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define ptr @test_simple_load_post(ptr %ptr) {
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; CHECK-LABEL: name: test_simple_load_post
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 0 :: (volatile load (i8) from %ir.ptr)
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; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%next = getelementptr i8, ptr %ptr, i32 42
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load volatile i8, ptr %ptr
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ret ptr %next
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}
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define ptr @test_simple_load_post_gep_after(ptr %ptr) {
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; CHECK-LABEL: name: test_simple_load_post_gep_after
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
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; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%offset = call i64 @get_offset()
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load volatile i8, ptr %ptr
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%next = getelementptr i8, ptr %ptr, i64 %offset
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ret ptr %next
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}
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define ptr @test_load_post_keep_looking(ptr %ptr) {
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; CHECK-LABEL: name: test_load_post_keep_looking
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
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; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[PTRTOINT]](i64)
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; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var
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; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var
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; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[ADD_LOW]](p0) :: (store (i8) into @var)
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; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%offset = call i64 @get_offset()
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load volatile i8, ptr %ptr
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%intval = ptrtoint ptr %ptr to i8
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store i8 %intval, ptr @var
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%next = getelementptr i8, ptr %ptr, i64 %offset
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ret ptr %next
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}
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; Base is frame index. Using indexing would need copy anyway.
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define ptr @test_load_post_alloca() {
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; CHECK-LABEL: name: test_load_post_alloca
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[FRAME_INDEX]](p0) :: (volatile dereferenceable load (i8) from %ir.ptr)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%ptr = alloca i8, i32 128
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%next = getelementptr i8, ptr %ptr, i32 42
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load volatile i8, ptr %ptr
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ret ptr %next
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}
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; Offset computation does not dominate the load we might be indexing.
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define ptr @test_load_post_gep_offset_after(ptr %ptr) {
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; CHECK-LABEL: name: test_load_post_gep_offset_after
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (volatile load (i8) from %ir.ptr)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[COPY1]](i64)
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; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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load volatile i8, ptr %ptr
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%offset = call i64 @get_offset()
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%next = getelementptr i8, ptr %ptr, i64 %offset
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ret ptr %next
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}
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declare void @bar(ptr)
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declare i64 @get_offset()
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@var = global i8 0
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@varp8 = global ptr null
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