derek.holloway
7502bf64a4
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392 lines
14 KiB
YAML
392 lines
14 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify the following:
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#
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# - We can fold compares into selects.
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# - This only happens when the result of the compare is only used by selects.
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#
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# Also verify that, for now:
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#
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# - We only support condition flags that require a single instruction.
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#
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...
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---
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name: fcmp_more_than_one_user_no_fold
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1, $w1
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; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold
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; CHECK: liveins: $s0, $s1, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
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; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(oeq), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %2, %1
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$w1 = COPY %5(i32)
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fcmp_more_than_one_select
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1, $w1
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; CHECK-LABEL: name: fcmp_more_than_one_select
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; CHECK: liveins: $s0, $s1, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(oeq), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %2, %1
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%7:fpr(f32) = G_SELECT %5, %1, %2
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$s0 = COPY %4(f32)
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$s1 = COPY %7(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: using_icmp
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $w0
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; CHECK-LABEL: name: using_icmp
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; CHECK: liveins: $s0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:gpr(i32) = COPY $w0
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%1:fpr(f32) = COPY $s0
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%2:gpr(i32) = G_CONSTANT i32 0
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%5:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%6:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
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%4:fpr(f32) = G_SELECT %6, %1, %5
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: foeq
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: foeq
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(oeq), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %2, %1
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fueq
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fueq
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(ueq), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %2, %1
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fone
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fone
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
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; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(one), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %1, %2
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fune
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fune
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(une), %0(f32), %2
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%4:fpr(f32) = G_SELECT %5, %1, %2
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$s0 = COPY %4(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: doeq
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: doeq
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
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; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:fpr(f64) = COPY $d0
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%1:fpr(f64) = COPY $d1
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%2:fpr(f64) = G_FCONSTANT double 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
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%4:fpr(f64) = G_SELECT %5, %2, %1
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$d0 = COPY %4(f64)
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RET_ReallyLR implicit $d0
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...
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---
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name: dueq
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: dueq
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
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; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
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; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:fpr(f64) = COPY $d0
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%1:fpr(f64) = COPY $d1
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%2:fpr(f64) = G_FCONSTANT double 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(ueq), %0(f64), %2
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%4:fpr(f64) = G_SELECT %5, %2, %1
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$d0 = COPY %4(f64)
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RET_ReallyLR implicit $d0
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...
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---
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name: done
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: done
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
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; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
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; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
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; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:fpr(f64) = COPY $d0
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%1:fpr(f64) = COPY $d1
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%2:fpr(f64) = G_FCONSTANT double 0.000000e+00
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%5:gpr(i32) = G_FCMP floatpred(one), %0(f64), %2
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%4:fpr(f64) = G_SELECT %5, %1, %2
|
|
$d0 = COPY %4(f64)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: dune
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
|
|
; CHECK-LABEL: name: dune
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
|
; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
|
|
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
|
|
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(f64) = COPY $d0
|
|
%1:fpr(f64) = COPY $d1
|
|
%2:fpr(f64) = G_FCONSTANT double 0.000000e+00
|
|
%5:gpr(i32) = G_FCMP floatpred(une), %0(f64), %2
|
|
%4:fpr(f64) = G_SELECT %5, %1, %2
|
|
$d0 = COPY %4(f64)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: copy_from_physreg
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $w0, $w1
|
|
|
|
; CHECK-LABEL: name: copy_from_physreg
|
|
; CHECK: liveins: $s0, $w0, $w1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
|
|
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
|
|
; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[FMOVS0_]]
|
|
; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY1]], 0, implicit-def $nzcv
|
|
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY]], [[FMOVS0_]], 1, implicit $nzcv
|
|
; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
|
|
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $s0
|
|
%0:gpr(f32) = COPY $w0
|
|
%1:fpr(f32) = COPY $s0
|
|
%5:fpr(f32) = G_FCONSTANT float 0.000000e+00
|
|
BL @copy_from_physreg, implicit-def $w0
|
|
%4:fpr(f32) = G_SELECT %5, %1, %5
|
|
BL @copy_from_physreg, implicit-def $w0
|
|
$s0 = COPY %4(f32)
|
|
RET_ReallyLR implicit $s0
|
|
|
|
...
|