derek.holloway
7502bf64a4
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258 lines
10 KiB
YAML
258 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define void @test_ms1(ptr nocapture %dst, i32 %c, i32 %len) local_unnamed_addr #0 {
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entry:
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%0 = trunc i32 %c to i8
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%conv = zext i32 %len to i64
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 %conv, i1 false)
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ret void
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}
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declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1
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define void @test_ms2_const(ptr nocapture %dst, i32 %c) local_unnamed_addr #0 {
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entry:
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%0 = trunc i32 %c to i8
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 16, i1 false)
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ret void
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}
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define void @test_zero_const(ptr nocapture %dst) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 0, i64 64, i1 false)
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ret void
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}
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define void @test_ms3_const_both(ptr nocapture %dst) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 64, i64 16, i1 false)
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ret void
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}
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define void @test_ms_vector(ptr nocapture %dst, i32 %c) local_unnamed_addr #0 {
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entry:
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%0 = trunc i32 %c to i8
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 16, i1 false)
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ret void
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}
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define void @test_ms4_const_both_unaligned(ptr nocapture %dst) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 64, i64 18, i1 false)
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ret void
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}
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define void @minsize(ptr nocapture %dst) minsize { unreachable }
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declare void @llvm.stackprotector(ptr, ptr) #2
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attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2" "use-soft-float"="false" }
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attributes #1 = { argmemonly nounwind }
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...
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---
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name: test_ms1
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w1, $w2, $x0
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; CHECK-LABEL: name: test_ms1
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; CHECK: liveins: $w1, $w2, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK-NEXT: G_MEMSET [[COPY]](p0), [[TRUNC]](s8), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%2:_(s32) = COPY $w2
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s64) = G_ZEXT %2(s32)
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G_MEMSET %0(p0), %3(s8), %4(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: test_ms2_const
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w1, $x0
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; CHECK-LABEL: name: test_ms2_const
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%3:_(s64) = G_CONSTANT i64 16
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%2:_(s8) = G_TRUNC %1(s32)
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G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: test_zero_const
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w1, $x0
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; CHECK-LABEL: name: test_zero_const
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 48, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = G_CONSTANT i32 0
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%3:_(s64) = G_CONSTANT i64 64
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%2:_(s8) = G_TRUNC %1(s32)
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G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: test_ms3_const_both
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_ms3_const_both
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_CONSTANT i8 64
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%2:_(s64) = G_CONSTANT i64 16
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G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: test_ms_vector
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w1, $x0
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; CHECK-LABEL: name: test_ms_vector
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 44, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%3:_(s64) = G_CONSTANT i64 60
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%2:_(s8) = G_TRUNC %1(s32)
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G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: test_ms4_const_both_unaligned
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_ms4_const_both_unaligned
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 16448
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
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; CHECK-NEXT: G_STORE [[C1]](i16), [[PTR_ADD]](p0) :: (store (i16) into %ir.dst + 16, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_CONSTANT i8 64
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%2:_(s64) = G_CONSTANT i64 18
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G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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...
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---
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name: minsize
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w1, $x0
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; CHECK-LABEL: name: minsize
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
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; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%3:_(s64) = G_CONSTANT i64 16
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%2:_(s8) = G_TRUNC %1(s32)
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G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
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RET_ReallyLR
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