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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

351 lines
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
define void @or_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_select
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[C2]], [[ICMP]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
%tmp4 = select i1 %tmp3, i1 true, i1 %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i1) = G_AND [[ICMP1]], [[ICMP]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
%tmp4 = and i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
define void @and_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond_select
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[ICMP]], [[C2]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
%tmp4 = select i1 %tmp3, i1 %tmp1, i1 false
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
; Don't emit two branches for same operands.
define void @or_cond_same_values_cmp(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_same_values_cmp
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
%tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
; Emit multiple branches for more than 2 cases.
define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_multiple_cases
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x10000000), %bb.5(0x70000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i1) = G_OR [[OR]], [[ICMP2]]
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.entry:
; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
%tmpZ = icmp eq i32 %Z, 5
%tmp4 = or i1 %tmp3, %tmp1
%final = or i1 %tmp4, %tmpZ
br i1 %final, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
; (X != null) | (Y != null) --> (X|Y) != 0
; Don't emit two branches.
define void @or_cond_ne_null(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_ne_null
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY1]](i32), [[C]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp ne i32 %X, 0
%tmp3 = icmp ne i32 %Y, 0
%tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
; If the branch is unpredictable, don't add another branch
; regardless of whether they are expensive or not.
define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: unpredictable
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.common.ret:
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cond_true:
; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock, !unpredictable !0
cond_true:
%tmp5 = tail call i32 (...) @bar( )
ret void
UnifiedReturnBlock:
ret void
}
!0 = !{}
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