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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -stop-after=irtranslator -mtriple=aarch64-- -verify-machineinstrs -o - %s | FileCheck %s
define i16 @smul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[SMULFIX:%[0-9]+]]:_(i16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIX]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @umul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[UMULFIX:%[0-9]+]]:_(i16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIX]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix_sat
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[SMULFIXSAT:%[0-9]+]]:_(i16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIXSAT]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix_sat
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[UMULFIXSAT:%[0-9]+]]:_(i16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIXSAT]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[SDIVFIX:%[0-9]+]]:_(i16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIX]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @udiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[UDIVFIX:%[0-9]+]]:_(i16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIX]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[SDIVFIXSAT:%[0-9]+]]:_(i16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIXSAT]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
define i16 @udiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; CHECK-NEXT: [[UDIVFIXSAT:%[0-9]+]]:_(i16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIXSAT]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
declare i16 @llvm.smul.fix.i16(i16, i16, i32 immarg) #0
declare i16 @llvm.umul.fix.i16(i16, i16, i32 immarg) #0
declare i16 @llvm.smul.fix.sat.i16(i16, i16, i32 immarg) #0
declare i16 @llvm.umul.fix.sat.i16(i16, i16, i32 immarg) #0
declare i16 @llvm.sdiv.fix.i16(i16, i16, i32 immarg) #1
declare i16 @llvm.udiv.fix.i16(i16, i16, i32 immarg) #1
declare i16 @llvm.sdiv.fix.sat.i16(i16, i16, i32 immarg) #1
declare i16 @llvm.udiv.fix.sat.i16(i16, i16, i32 immarg) #1
attributes #0 = { nounwind readnone speculatable willreturn }
attributes #1 = { nounwind readnone }
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