derek.holloway
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83 lines
3.2 KiB
LLVM
83 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
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define i32 @load_invariant(ptr %ptr) {
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; CHECK-LABEL: name: load_invariant
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load i32, ptr %ptr, align 4, !invariant.load !0
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ret i32 %load
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}
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define i32 @load_volatile_invariant(ptr %ptr) {
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; CHECK-LABEL: name: load_volatile_invariant
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load volatile i32, ptr %ptr, align 4, !invariant.load !0
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ret i32 %load
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}
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define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {
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; CHECK-LABEL: name: load_dereferenceable
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load i32, ptr %ptr, align 4
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ret i32 %load
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}
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define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {
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; CHECK-LABEL: name: load_dereferenceable_invariant
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load i32, ptr %ptr, align 4, !invariant.load !0
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ret i32 %load
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}
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define i32 @load_nontemporal(ptr %ptr) {
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; CHECK-LABEL: name: load_nontemporal
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (non-temporal load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load i32, ptr %ptr, align 4, !nontemporal !0
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ret i32 %load
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}
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define i32 @load_falkor_strided_access(ptr %ptr) {
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; CHECK-LABEL: name: load_falkor_strided_access
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (i32) from %ir.ptr)
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; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%load = load i32, ptr %ptr, align 4, !falkor.strided.access !0
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ret i32 %load
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}
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!0 = !{}
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