derek.holloway
7502bf64a4
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134 lines
5.6 KiB
LLVM
134 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s
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define void @copy(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: copy
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
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ret void
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}
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define void @inline_copy(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: inline_copy
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
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ret void
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}
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define void @copy_volatile(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: copy_volatile
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
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ret void
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}
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define void @inline_copy_volatile(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: inline_copy_volatile
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
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ret void
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}
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define void @tail_copy(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: tail_copy
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
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ret void
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}
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define void @tail_inline_copy(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: tail_inline_copy
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
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ret void
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}
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define void @tail_copy_volatile(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: tail_copy_volatile
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
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ret void
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}
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define void @tail_inline_copy_volatile(ptr %dst, ptr %src) {
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; CHECK-LABEL: name: tail_inline_copy_volatile
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
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; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
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ret void
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}
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declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) nounwind
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declare void @llvm.memcpy.inline.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) nounwind
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