derek.holloway
7502bf64a4
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360 lines
17 KiB
YAML
360 lines
17 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_scalar_and_small
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_and_small
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; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[TRUNC1]]
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; CHECK-NEXT: $w0 = COPY [[AND]](i32)
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; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
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%0:_(i64) = COPY $x0
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%1:_(i64) = COPY $x1
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%2:_(i8) = G_TRUNC %0(i64)
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%3:_(i8) = G_TRUNC %1(i64)
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%4:_(i8) = G_AND %2, %3
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%6:_(i32) = G_ANYEXT %4(i8)
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$w0 = COPY %6(i32)
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%5:_(i64) = G_ANYEXT %2(i8)
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$x0 = COPY %5(i64)
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...
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---
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name: test_nonpow2
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_nonpow2
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from unknown-address + 8, align 8)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
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; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](i32)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i64) = G_OR [[C]], [[LOAD]]
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; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i64) = G_OR [[OR]], [[C]]
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; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
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; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
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; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 10, align 2)
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; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](i32)
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; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s64)
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; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD1]]
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; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i64) = G_OR [[C]], [[LOAD2]]
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; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i64) = G_OR [[OR3]], [[C]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[OR1]], [[OR4]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[OR2]], [[OR5]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[AND1]](i64)
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; CHECK-NEXT: G_STORE [[COPY1]](i64), %ptr(p0) :: (store (i64), align 16)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
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; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C5]](i64)
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; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
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; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C6]](i64)
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; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8)
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; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2)
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%ptr:_(p0) = COPY $x0
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%a:_(i88) = G_LOAD %ptr(p0) :: (load (s88))
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%b:_(i88) = G_LOAD %ptr(p0) :: (load (s88))
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%and:_(i88) = G_AND %a, %b
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G_STORE %and(i88), %ptr(p0) :: (store (s88))
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...
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---
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name: test_s318_and
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_s318_and
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: %ptr:_(p0) = COPY $x0
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
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; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[AND]], [[C]]
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; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[AND1]], [[C]]
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; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[AND2]], [[C]]
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; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i64) = G_AND [[AND3]], [[C]]
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; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i64) = G_AND [[AND4]], [[C1]]
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; CHECK-NEXT: G_STORE [[AND5]](i64), %ptr(p0) :: (store (i64), align 64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
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; CHECK-NEXT: G_STORE [[AND6]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
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; CHECK-NEXT: G_STORE [[AND7]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
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; CHECK-NEXT: G_STORE [[AND8]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
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; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
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; CHECK-NEXT: G_STORE [[AND9]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%a:_(s318) = G_IMPLICIT_DEF
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%b:_(s318) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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%and:_(s318) = G_AND %a, %b
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G_STORE %and(s318), %ptr(p0) :: (store (s318))
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RET_ReallyLR implicit $x0
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...
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---
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name: test_s158_and
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_s158_and
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: %ptr:_(p0) = COPY $x0
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
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; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[AND]], [[C]]
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; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[AND1]], [[C]]
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; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[AND2]], [[C]]
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; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i64) = G_AND [[AND3]], [[C]]
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; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i64) = G_AND [[AND4]], [[C1]]
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; CHECK-NEXT: G_STORE [[AND5]](i64), %ptr(p0) :: (store (i64), align 64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
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; CHECK-NEXT: G_STORE [[AND6]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
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; CHECK-NEXT: G_STORE [[AND7]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
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; CHECK-NEXT: G_STORE [[AND8]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
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; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
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; CHECK-NEXT: G_STORE [[AND9]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%a:_(s318) = G_IMPLICIT_DEF
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%b:_(s318) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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%and:_(s318) = G_AND %a, %b
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G_STORE %and(s318), %ptr(p0) :: (store (s318))
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RET_ReallyLR implicit $x0
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...
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---
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name: test_vector_and_v16s16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_vector_and_v16s16
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i16>) = COPY $q1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x i16>) = G_AND [[COPY]], [[COPY]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x i16>) = G_AND [[COPY1]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[AND]](<8 x i16>)
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; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x i16>)
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%1:_(<8 x i16>) = COPY $q0
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%2:_(<8 x i16>) = COPY $q1
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%0:_(<16 x i16>) = G_CONCAT_VECTORS %1(<8 x i16>), %2(<8 x i16>)
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%3:_(<16 x i16>) = G_AND %0, %0
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%4:_(<8 x i16>), %5:_(<8 x i16>) = G_UNMERGE_VALUES %3(<16 x i16>)
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$q0 = COPY %4(<8 x i16>)
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$q1 = COPY %5(<8 x i16>)
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...
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---
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name: test_vector_and_v32s8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_vector_and_v32s8
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x i8>) = G_AND [[COPY]], [[COPY]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x i8>) = G_AND [[COPY1]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[AND]](<16 x i8>)
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; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x i8>)
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%0:_(<16 x i8>) = COPY $q0
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%1:_(<16 x i8>) = COPY $q1
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%2:_(<32 x i8>) = G_CONCAT_VECTORS %0, %1
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%3:_(<32 x i8>) = G_AND %2, %2
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%7:_(<16 x i8>), %8:_(<16 x i8>) = G_UNMERGE_VALUES %3(<32 x i8>)
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$q0 = COPY %7(<16 x i8>)
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$q1 = COPY %8(<16 x i8>)
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...
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---
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name: and_v2s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $d2, $d3
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; CHECK-LABEL: name: and_v2s1
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; CHECK: liveins: $d0, $d1, $d2, $d3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i32>) = COPY $d2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i32>) = COPY $d3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i32>) = G_ICMP intpred(eq), [[COPY]](<2 x i32>), [[COPY1]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i32>) = G_ICMP intpred(eq), [[COPY2]](<2 x i32>), [[COPY3]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: $d0 = COPY [[AND]](<2 x i32>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:_(<2 x i32>) = COPY $d0
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%1:_(<2 x i32>) = COPY $d1
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%2:_(<2 x i32>) = COPY $d2
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%3:_(<2 x i32>) = COPY $d3
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%4:_(<2 x i1>) = G_ICMP intpred(eq), %0(<2 x i32>), %1
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%5:_(<2 x i1>) = G_ICMP intpred(eq), %2(<2 x i32>), %3
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%6:_(<2 x i1>) = G_AND %4, %5
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%7:_(<2 x i32>) = G_ANYEXT %6
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$d0 = COPY %7:_(<2 x i32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: and_v3s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $b0, $b1, $b2
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; CHECK-LABEL: name: and_v3s1
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; CHECK: liveins: $b0, $b1, $b2
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; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i8) = COPY $b0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i8) = COPY $b1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i8) = COPY $b2
|
|
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY]](i8)
|
|
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY1]](i8)
|
|
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY2]](i8)
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
|
|
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[ANYEXT]](i16), [[ANYEXT1]](i16), [[ANYEXT2]](i16), [[DEF]](i16)
|
|
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
|
|
; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[AND]](<4 x i16>)
|
|
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[UV]](i16)
|
|
; CHECK-NEXT: $b0 = COPY [[TRUNC]](i8)
|
|
; CHECK-NEXT: RET_ReallyLR implicit $b0
|
|
%1:_(i8) = COPY $b0
|
|
%2:_(i8) = COPY $b1
|
|
%3:_(i8) = COPY $b2
|
|
%4:_(<3 x i8>) = G_BUILD_VECTOR %1(i8), %2(i8), %3(i8)
|
|
%0:_(<3 x i1>) = G_TRUNC %4(<3 x i8>)
|
|
%5:_(<3 x i1>) = G_AND %0, %0
|
|
%7:_(<3 x i8>) = G_ANYEXT %5(<3 x i1>)
|
|
%8:_(i8), %9:_(i8), %10:_(i8) = G_UNMERGE_VALUES %7(<3 x i8>)
|
|
$b0 = COPY %8:_(i8)
|
|
RET_ReallyLR implicit $b0
|
|
...
|
|
---
|
|
name: and_v4s1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $d0, $d1, $d2, $d3
|
|
|
|
; CHECK-LABEL: name: and_v4s1
|
|
; CHECK: liveins: $d0, $d1, $d2, $d3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i16>) = COPY $d1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i16>) = COPY $d2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x i16>) = COPY $d3
|
|
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x i16>) = G_ICMP intpred(eq), [[COPY]](<4 x i16>), [[COPY1]]
|
|
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x i16>) = G_ICMP intpred(eq), [[COPY2]](<4 x i16>), [[COPY3]]
|
|
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[ICMP]], [[ICMP1]]
|
|
; CHECK-NEXT: $d0 = COPY [[AND]](<4 x i16>)
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:_(<4 x i16>) = COPY $d0
|
|
%1:_(<4 x i16>) = COPY $d1
|
|
%2:_(<4 x i16>) = COPY $d2
|
|
%3:_(<4 x i16>) = COPY $d3
|
|
%4:_(<4 x i1>) = G_ICMP intpred(eq), %0(<4 x i16>), %1
|
|
%5:_(<4 x i1>) = G_ICMP intpred(eq), %2(<4 x i16>), %3
|
|
%6:_(<4 x i1>) = G_AND %4, %5
|
|
%7:_(<4 x i16>) = G_ANYEXT %6
|
|
$d0 = COPY %7:_(<4 x i16>)
|
|
RET_ReallyLR implicit $d0
|
|
...
|
|
---
|
|
name: and_v8s1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $d0, $d1, $d2, $d3
|
|
|
|
; CHECK-LABEL: name: and_v8s1
|
|
; CHECK: liveins: $d0, $d1, $d2, $d3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x i8>) = COPY $d2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x i8>) = COPY $d3
|
|
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x i8>) = G_ICMP intpred(eq), [[COPY]](<8 x i8>), [[COPY1]]
|
|
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x i8>) = G_ICMP intpred(eq), [[COPY2]](<8 x i8>), [[COPY3]]
|
|
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x i8>) = G_AND [[ICMP]], [[ICMP1]]
|
|
; CHECK-NEXT: $d0 = COPY [[AND]](<8 x i8>)
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:_(<8 x i8>) = COPY $d0
|
|
%1:_(<8 x i8>) = COPY $d1
|
|
%2:_(<8 x i8>) = COPY $d2
|
|
%3:_(<8 x i8>) = COPY $d3
|
|
%4:_(<8 x i1>) = G_ICMP intpred(eq), %0(<8 x i8>), %1
|
|
%5:_(<8 x i1>) = G_ICMP intpred(eq), %2(<8 x i8>), %3
|
|
%6:_(<8 x i1>) = G_AND %4, %5
|
|
%7:_(<8 x i8>) = G_ANYEXT %6
|
|
$d0 = COPY %7:_(<8 x i8>)
|
|
RET_ReallyLR implicit $d0
|
|
...
|
|
---
|
|
name: and_v16s1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $q0, $q1, $q2, $q3
|
|
|
|
; CHECK-LABEL: name: and_v16s1
|
|
; CHECK: liveins: $q0, $q1, $q2, $q3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x i8>) = COPY $q2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x i8>) = COPY $q3
|
|
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x i8>) = G_ICMP intpred(eq), [[COPY]](<16 x i8>), [[COPY1]]
|
|
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x i8>) = G_ICMP intpred(eq), [[COPY2]](<16 x i8>), [[COPY3]]
|
|
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x i8>) = G_AND [[ICMP]], [[ICMP1]]
|
|
; CHECK-NEXT: $q0 = COPY [[AND]](<16 x i8>)
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<16 x i8>) = COPY $q0
|
|
%1:_(<16 x i8>) = COPY $q1
|
|
%2:_(<16 x i8>) = COPY $q2
|
|
%3:_(<16 x i8>) = COPY $q3
|
|
%4:_(<16 x i1>) = G_ICMP intpred(eq), %0(<16 x i8>), %1
|
|
%5:_(<16 x i1>) = G_ICMP intpred(eq), %2(<16 x i8>), %3
|
|
%6:_(<16 x i1>) = G_AND %4, %5
|
|
%7:_(<16 x i8>) = G_ANYEXT %6
|
|
$q0 = COPY %7:_(<16 x i8>)
|
|
RET_ReallyLR implicit $q0
|
|
...
|