derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

334 lines
17 KiB
YAML
Raw Blame History

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
# RUN: | FileCheck %s
...
---
name: test_v4f16.atan2
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_v4f16.atan2
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $d1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16), [[UV6:%[0-9]+]]:_(f16), [[UV7:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV4]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT1]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY2]](f32)
; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV5]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT2]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT3]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY3]](f32)
; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[UV6]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT4]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT5]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY4]](f32)
; CHECK-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
; CHECK-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[UV7]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT6]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT7]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY5]](f32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16), [[FPTRUNC2]](f16), [[FPTRUNC3]](f16)
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x f16>) = COPY $d0
%1:_(<4 x f16>) = COPY $d1
%2:_(<4 x f16>) = G_FATAN2 %0, %1
$d0 = COPY %2(<4 x f16>)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.atan2
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_v8f16.atan2
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16), [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16), [[UV6:%[0-9]+]]:_(f16), [[UV7:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(f16), [[UV9:%[0-9]+]]:_(f16), [[UV10:%[0-9]+]]:_(f16), [[UV11:%[0-9]+]]:_(f16), [[UV12:%[0-9]+]]:_(f16), [[UV13:%[0-9]+]]:_(f16), [[UV14:%[0-9]+]]:_(f16), [[UV15:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY1]](<8 x f16>)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV8]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT1]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY2]](f32)
; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV9]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT2]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT3]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY3]](f32)
; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[UV10]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT4]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT5]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY4]](f32)
; CHECK-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
; CHECK-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[UV11]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT6]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT7]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY5]](f32)
; CHECK-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[UV4]](f16)
; CHECK-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[UV12]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT8]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT9]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY6]](f32)
; CHECK-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[UV5]](f16)
; CHECK-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[UV13]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT10]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT11]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY7]](f32)
; CHECK-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[UV6]](f16)
; CHECK-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[UV14]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT12]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT13]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY8]](f32)
; CHECK-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = G_FPEXT [[UV7]](f16)
; CHECK-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = G_FPEXT [[UV15]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT14]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT15]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY9]](f32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16), [[FPTRUNC2]](f16), [[FPTRUNC3]](f16), [[FPTRUNC4]](f16), [[FPTRUNC5]](f16), [[FPTRUNC6]](f16), [[FPTRUNC7]](f16)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<8 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x f16>) = COPY $q0
%1:_(<8 x f16>) = COPY $q1
%2:_(<8 x f16>) = G_FATAN2 %0, %1
$q0 = COPY %2(<8 x f16>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f32.atan2
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_v2f32.atan2
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $d1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV]](f32)
; CHECK-NEXT: $s1 = COPY [[UV2]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV1]](f32)
; CHECK-NEXT: $s1 = COPY [[UV3]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY2]](f32), [[COPY3]](f32)
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x f32>) = COPY $d0
%1:_(<2 x f32>) = COPY $d1
%2:_(<2 x f32>) = G_FATAN2 %0, %1
$d0 = COPY %2(<2 x f32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.atan2
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_v4f32.atan2
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV]](f32)
; CHECK-NEXT: $s1 = COPY [[UV4]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV1]](f32)
; CHECK-NEXT: $s1 = COPY [[UV5]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV2]](f32)
; CHECK-NEXT: $s1 = COPY [[UV6]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV3]](f32)
; CHECK-NEXT: $s1 = COPY [[UV7]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY2]](f32), [[COPY3]](f32), [[COPY4]](f32), [[COPY5]](f32)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x f32>) = COPY $q0
%1:_(<4 x f32>) = COPY $q1
%2:_(<4 x f32>) = G_FATAN2 %0, %1
$q0 = COPY %2(<4 x f32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.atan2
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_v2f64.atan2
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $d0 = COPY [[UV]](f64)
; CHECK-NEXT: $d1 = COPY [[UV2]](f64)
; CHECK-NEXT: BL &atan2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $d0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $d0 = COPY [[UV1]](f64)
; CHECK-NEXT: $d1 = COPY [[UV3]](f64)
; CHECK-NEXT: BL &atan2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f64) = COPY $d0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[COPY2]](f64), [[COPY3]](f64)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x f64>) = COPY $q0
%1:_(<2 x f64>) = COPY $q1
%2:_(<2 x f64>) = G_FATAN2 %0, %1
$q0 = COPY %2(<2 x f64>)
RET_ReallyLR implicit $q0
...
---
name: test_atan2_half
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $h0, $h1
; CHECK-LABEL: name: test_atan2_half
; CHECK: liveins: $h0, $h1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f16) = COPY $h1
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[COPY]](f16)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[COPY1]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: $s1 = COPY [[FPEXT1]](f32)
; CHECK-NEXT: BL &atan2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY2]](f32)
; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:_(f16) = COPY $h0
%1:_(f16) = COPY $h1
%2:_(f16) = G_FATAN2 %0, %1
$h0 = COPY %2(f16)
RET_ReallyLR implicit $h0
Reference in new issue View Git Blame Copy Permalink