TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s

---
name:            legal_v4s32_v2s32
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: legal_v4s32_v2s32
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[COPY1]](<2 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR
...
---
name:            legal_v8s16_v4s16
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: legal_v8s16_v4s16
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>)
    ; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
    $q0 = COPY %2(<8 x s16>)
    RET_ReallyLR
...
---
name:            legal_v16s8_v8s8
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: legal_v16s8_v8s8
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %b:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %concat:_(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
    ; CHECK-NEXT: $q0 = COPY %concat(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %a:_(<8 x s8>) = G_IMPLICIT_DEF
    %b:_(<8 x s8>) = G_IMPLICIT_DEF
    %concat:_(<16 x s8>) = G_CONCAT_VECTORS %a:_(<8 x s8>), %b:_(<8 x s8>)
    $q0 = COPY %concat(<16 x s8>)
    RET_ReallyLR implicit $q0
...
---
name:            illegal_v16s8_v4s8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: illegal_v16s8_v4s8
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(p0) = COPY $x0
    ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
    ; CHECK-NEXT: %c:_(<4 x s8>) = G_BITCAST %b(s32)
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[BUILD_VECTOR]](<8 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[TRUNC]](<8 x s8>)
    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<4 x s8>)
    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<4 x s8>)
    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<4 x s8>)
    ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<4 x s8>)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[BITCAST1]](s32), [[BITCAST2]](s32), [[BITCAST3]](s32)
    ; CHECK-NEXT: %f:_(<16 x s8>) = G_BITCAST [[BUILD_VECTOR1]](<4 x s32>)
    ; CHECK-NEXT: $q0 = COPY %f(<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %a:_(p0) = COPY $x0
    %b:_(s32) = G_LOAD %a:_(p0) :: (load (s32))
    %c:_(<4 x s8>) = G_BITCAST %b:_(s32)
    %d:_(s8) = G_IMPLICIT_DEF
    %e:_(<4 x s8>) = G_BUILD_VECTOR %d:_(s8), %d:_(s8), %d:_(s8), %d:_(s8)
    %f:_(<16 x s8>) = G_CONCAT_VECTORS %c:_(<4 x s8>), %e:_(<4 x s8>), %e:_(<4 x s8>), %e:_(<4 x s8>)

    $q0 = COPY %f(<16 x s8>)
    RET_ReallyLR implicit $q0
...
---
name:            illegal_v8s16_v2s16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: illegal_v8s16_v2s16
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %a:_(p0) = COPY $x0
    ; CHECK-NEXT: %b:_(s32) = G_LOAD %a(p0) :: (load (s32))
    ; CHECK-NEXT: %c:_(<2 x s16>) = G_BITCAST %b(s32)
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[TRUNC]](<4 x s16>)
    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST %c(<2 x s16>)
    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
    ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[BITCAST1]](s32), [[BITCAST2]](s32), [[BITCAST3]](s32)
    ; CHECK-NEXT: %f:_(<8 x s16>) = G_BITCAST [[BUILD_VECTOR1]](<4 x s32>)
    ; CHECK-NEXT: $q0 = COPY %f(<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %a:_(p0) = COPY $x0
    %b:_(s32) = G_LOAD %a:_(p0) :: (load (s32))
    %c:_(<2 x s16>) = G_BITCAST %b:_(s32)
    %d:_(s16) = G_IMPLICIT_DEF
    %e:_(<2 x s16>) = G_BUILD_VECTOR %d:_(s16), %d:_(s16)
    %f:_(<8 x s16>) = G_CONCAT_VECTORS %c:_(<2 x s16>), %e:_(<2 x s16>), %e:_(<2 x s16>), %e:_(<2 x s16>)

    $q0 = COPY %f(<8 x s16>)
    RET_ReallyLR implicit $q0
...