derek.holloway
7502bf64a4
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200 lines
8.3 KiB
YAML
200 lines
8.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
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...
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---
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name: test_v4f16.fma
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $d1, $d2
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; NO-FP16-LABEL: name: test_v4f16.fma
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; NO-FP16: liveins: $d0, $d1, $d2
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; NO-FP16-NEXT: {{ $}}
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; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
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; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $d1
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; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $d2
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; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x f16>)
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; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY1]](<4 x f16>)
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; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY2]](<4 x f16>)
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; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x f32>) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
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; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[FMA]](<4 x f32>)
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; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x f16>)
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; NO-FP16-NEXT: RET_ReallyLR implicit $d0
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;
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; FP16-LABEL: name: test_v4f16.fma
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; FP16: liveins: $d0, $d1, $d2
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; FP16-NEXT: {{ $}}
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; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
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; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $d1
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; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $d2
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; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x f16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; FP16-NEXT: $d0 = COPY [[FMA]](<4 x f16>)
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; FP16-NEXT: RET_ReallyLR implicit $d0
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%0:_(<4 x f16>) = COPY $d0
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%1:_(<4 x f16>) = COPY $d1
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%2:_(<4 x f16>) = COPY $d2
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%3:_(<4 x f16>) = G_FMA %0, %1, %2
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$d0 = COPY %3(<4 x f16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.fma
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; NO-FP16-LABEL: name: test_v8f16.fma
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; NO-FP16: liveins: $q0, $q1, $q2
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; NO-FP16-NEXT: {{ $}}
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; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
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; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
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; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x f16>) = COPY $q2
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; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x f16>), [[UV1:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
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; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x f16>)
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; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x f16>)
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; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<4 x f16>), [[UV3:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY1]](<8 x f16>)
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; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV2]](<4 x f16>)
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; NO-FP16-NEXT: [[FPEXT3:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV3]](<4 x f16>)
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; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(<4 x f16>), [[UV5:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY2]](<8 x f16>)
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; NO-FP16-NEXT: [[FPEXT4:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV4]](<4 x f16>)
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; NO-FP16-NEXT: [[FPEXT5:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV5]](<4 x f16>)
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; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x f32>) = G_FMA [[FPEXT]], [[FPEXT2]], [[FPEXT4]]
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; NO-FP16-NEXT: [[FMA1:%[0-9]+]]:_(<4 x f32>) = G_FMA [[FPEXT1]], [[FPEXT3]], [[FPEXT5]]
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; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[FMA]](<4 x f32>)
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; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[FMA1]](<4 x f32>)
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; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x f16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x f16>), [[FPTRUNC1]](<4 x f16>)
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; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x f16>)
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; NO-FP16-NEXT: RET_ReallyLR implicit $q0
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;
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; FP16-LABEL: name: test_v8f16.fma
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; FP16: liveins: $q0, $q1, $q2
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; FP16-NEXT: {{ $}}
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; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
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; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
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; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x f16>) = COPY $q2
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; FP16-NEXT: [[FMA:%[0-9]+]]:_(<8 x f16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; FP16-NEXT: $q0 = COPY [[FMA]](<8 x f16>)
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; FP16-NEXT: RET_ReallyLR implicit $q0
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%0:_(<8 x f16>) = COPY $q0
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%1:_(<8 x f16>) = COPY $q1
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%2:_(<8 x f16>) = COPY $q2
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%3:_(<8 x f16>) = G_FMA %0, %1, %2
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$q0 = COPY %3(<8 x f16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.fma
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $d1, $d2
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; NO-FP16-LABEL: name: test_v2f32.fma
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; NO-FP16: liveins: $d0, $d1, $d2
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; NO-FP16-NEXT: {{ $}}
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; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
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; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $d1
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; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $d2
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; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x f32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; NO-FP16-NEXT: $d0 = COPY [[FMA]](<2 x f32>)
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; NO-FP16-NEXT: RET_ReallyLR implicit $d0
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;
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; FP16-LABEL: name: test_v2f32.fma
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; FP16: liveins: $d0, $d1, $d2
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; FP16-NEXT: {{ $}}
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; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
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; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $d1
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; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $d2
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; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x f32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; FP16-NEXT: $d0 = COPY [[FMA]](<2 x f32>)
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; FP16-NEXT: RET_ReallyLR implicit $d0
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%0:_(<2 x f32>) = COPY $d0
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%1:_(<2 x f32>) = COPY $d1
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%2:_(<2 x f32>) = COPY $d2
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%3:_(<2 x f32>) = G_FMA %0, %1, %2
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$d0 = COPY %3(<2 x f32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.fma
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; NO-FP16-LABEL: name: test_v4f32.fma
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; NO-FP16: liveins: $q0, $q1, $q2
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; NO-FP16-NEXT: {{ $}}
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; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
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; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $q1
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; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $q2
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; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x f32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; NO-FP16-NEXT: $q0 = COPY [[FMA]](<4 x f32>)
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; NO-FP16-NEXT: RET_ReallyLR implicit $q0
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;
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; FP16-LABEL: name: test_v4f32.fma
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; FP16: liveins: $q0, $q1, $q2
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; FP16-NEXT: {{ $}}
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; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
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; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $q1
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; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $q2
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; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x f32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; FP16-NEXT: $q0 = COPY [[FMA]](<4 x f32>)
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; FP16-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x f32>) = COPY $q0
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%1:_(<4 x f32>) = COPY $q1
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%2:_(<4 x f32>) = COPY $q2
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%3:_(<4 x f32>) = G_FMA %0, %1, %2
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$q0 = COPY %3(<4 x f32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.fma
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; NO-FP16-LABEL: name: test_v2f64.fma
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; NO-FP16: liveins: $q0, $q1, $q2
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; NO-FP16-NEXT: {{ $}}
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; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
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; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $q1
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; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f64>) = COPY $q2
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; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x f64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; NO-FP16-NEXT: $q0 = COPY [[FMA]](<2 x f64>)
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; NO-FP16-NEXT: RET_ReallyLR implicit $q0
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;
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; FP16-LABEL: name: test_v2f64.fma
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; FP16: liveins: $q0, $q1, $q2
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; FP16-NEXT: {{ $}}
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; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
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; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $q1
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; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f64>) = COPY $q2
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; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x f64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
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; FP16-NEXT: $q0 = COPY [[FMA]](<2 x f64>)
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; FP16-NEXT: RET_ReallyLR implicit $q0
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%0:_(<2 x f64>) = COPY $q0
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%1:_(<2 x f64>) = COPY $q1
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%2:_(<2 x f64>) = COPY $q2
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%3:_(<2 x f64>) = G_FMA %0, %1, %2
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$q0 = COPY %3(<2 x f64>)
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RET_ReallyLR implicit $q0
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