TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s

...
---
name:            f16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $h0, $h1, $h2
    ; CHECK-LABEL: name: f16
    ; CHECK: liveins: $h0, $h1, $h2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(f16) = COPY $h0
    ; CHECK-NEXT: %op1:_(f16) = COPY $h1
    ; CHECK-NEXT: %op2:_(f16) = COPY $h2
    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT %op0(f16)
    ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT %op1(f16)
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
    ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
    ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT %op2(f16)
    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
    ; CHECK-NEXT: %fmad:_(f16) = G_FPTRUNC [[FADD]](f32)
    ; CHECK-NEXT: $h0 = COPY %fmad(f16)
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %op0:_(f16) = COPY $h0
    %op1:_(f16) = COPY $h1
    %op2:_(f16) = COPY $h2
    %fmad:_(f16) = G_FMAD %op0, %op1, %op2
    $h0 = COPY %fmad
    RET_ReallyLR implicit $h0
...
---
name:            f32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $s0, $s1, $s2
    ; CHECK-LABEL: name: f32
    ; CHECK: liveins: $s0, $s1, $s2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(f32) = COPY $s0
    ; CHECK-NEXT: %op1:_(f32) = COPY $s1
    ; CHECK-NEXT: %op2:_(f32) = COPY $s2
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL %op0, %op1
    ; CHECK-NEXT: %fmad:_(f32) = G_FADD [[FMUL]], %op2
    ; CHECK-NEXT: $s0 = COPY %fmad(f32)
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %op0:_(f32) = COPY $s0
    %op1:_(f32) = COPY $s1
    %op2:_(f32) = COPY $s2
    %fmad:_(f32) = G_FMAD %op0, %op1, %op2
    $s0 = COPY %fmad
    RET_ReallyLR implicit $s0
...
---
name:            f64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0, $d1, $d2
    ; CHECK-LABEL: name: f64
    ; CHECK: liveins: $d0, $d1, $d2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(f64) = COPY $d0
    ; CHECK-NEXT: %op1:_(f64) = COPY $d1
    ; CHECK-NEXT: %op2:_(f64) = COPY $d2
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL %op0, %op1
    ; CHECK-NEXT: %fmad:_(f64) = G_FADD [[FMUL]], %op2
    ; CHECK-NEXT: $d0 = COPY %fmad(f64)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %op0:_(f64) = COPY $d0
    %op1:_(f64) = COPY $d1
    %op2:_(f64) = COPY $d2
    %fmad:_(f64) = G_FMAD %op0, %op1, %op2
    $d0 = COPY %fmad
    RET_ReallyLR implicit $d0
...
---
name:            v2s32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0, $d1, $d2
    ; CHECK-LABEL: name: v2s32
    ; CHECK: liveins: $d0, $d1, $d2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(<2 x f32>) = COPY $d0
    ; CHECK-NEXT: %op1:_(<2 x f32>) = COPY $d1
    ; CHECK-NEXT: %op2:_(<2 x f32>) = COPY $d2
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x f32>) = G_FMUL %op0, %op1
    ; CHECK-NEXT: %fmad:_(<2 x f32>) = G_FADD [[FMUL]], %op2
    ; CHECK-NEXT: $d0 = COPY %fmad(<2 x f32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %op0:_(<2 x f32>) = COPY $d0
    %op1:_(<2 x f32>) = COPY $d1
    %op2:_(<2 x f32>) = COPY $d2
    %fmad:_(<2 x f32>) = G_FMAD %op0, %op1, %op2
    $d0 = COPY %fmad
    RET_ReallyLR implicit $d0
...
---
name:            v4s32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $q1, $q2
    ; CHECK-LABEL: name: v4s32
    ; CHECK: liveins: $q0, $q1, $q2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(<4 x f32>) = COPY $q0
    ; CHECK-NEXT: %op1:_(<4 x f32>) = COPY $q1
    ; CHECK-NEXT: %op2:_(<4 x f32>) = COPY $q2
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<4 x f32>) = G_FMUL %op0, %op1
    ; CHECK-NEXT: %fmad:_(<4 x f32>) = G_FADD [[FMUL]], %op2
    ; CHECK-NEXT: $q0 = COPY %fmad(<4 x f32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %op0:_(<4 x f32>) = COPY $q0
    %op1:_(<4 x f32>) = COPY $q1
    %op2:_(<4 x f32>) = COPY $q2
    %fmad:_(<4 x f32>) = G_FMAD %op0, %op1, %op2
    $q0 = COPY %fmad
    RET_ReallyLR implicit $q0
...
---
name:            v2s64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0, $q1, $q2
    ; CHECK-LABEL: name: v2s64
    ; CHECK: liveins: $q0, $q1, $q2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %op0:_(<2 x f64>) = COPY $q0
    ; CHECK-NEXT: %op1:_(<2 x f64>) = COPY $q1
    ; CHECK-NEXT: %op2:_(<2 x f64>) = COPY $q2
    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x f64>) = G_FMUL %op0, %op1
    ; CHECK-NEXT: %fmad:_(<2 x f64>) = G_FADD [[FMUL]], %op2
    ; CHECK-NEXT: $q0 = COPY %fmad(<2 x f64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %op0:_(<2 x f64>) = COPY $q0
    %op1:_(<2 x f64>) = COPY $q1
    %op2:_(<2 x f64>) = COPY $q2
    %fmad:_(<2 x f64>) = G_FMAD %op0, %op1, %op2
    $q0 = COPY %fmad
    RET_ReallyLR implicit $q0
...