derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
350 lines
13 KiB
YAML
350 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
|
|
# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
|
|
# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
|
|
|
|
...
|
|
---
|
|
name: test_f16.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $h0
|
|
|
|
; NO-FP16-LABEL: name: test_f16.roundeven
|
|
; NO-FP16: liveins: $h0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
|
|
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[COPY]](f16)
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]
|
|
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](f32)
|
|
; NO-FP16-NEXT: $h0 = COPY [[FPTRUNC]](f16)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
|
|
;
|
|
; FP16-LABEL: name: test_f16.roundeven
|
|
; FP16: liveins: $h0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f16) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $h0 = COPY [[INTRINSIC_ROUNDEVEN]](f16)
|
|
; FP16-NEXT: RET_ReallyLR implicit $h0
|
|
%0:_(f16) = COPY $h0
|
|
%1:_(f16) = G_INTRINSIC_ROUNDEVEN %0
|
|
$h0 = COPY %1(f16)
|
|
RET_ReallyLR implicit $h0
|
|
|
|
...
|
|
---
|
|
name: test_f32.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0
|
|
|
|
; NO-FP16-LABEL: name: test_f32.roundeven
|
|
; NO-FP16: liveins: $s0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: $s0 = COPY [[INTRINSIC_ROUNDEVEN]](f32)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $s0
|
|
;
|
|
; FP16-LABEL: name: test_f32.roundeven
|
|
; FP16: liveins: $s0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $s0 = COPY [[INTRINSIC_ROUNDEVEN]](f32)
|
|
; FP16-NEXT: RET_ReallyLR implicit $s0
|
|
%0:_(f32) = COPY $s0
|
|
%1:_(f32) = G_INTRINSIC_ROUNDEVEN %0
|
|
$s0 = COPY %1(f32)
|
|
RET_ReallyLR implicit $s0
|
|
|
|
...
|
|
---
|
|
name: test_f64.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
; NO-FP16-LABEL: name: test_f64.roundeven
|
|
; NO-FP16: liveins: $d0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](f64)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
|
|
;
|
|
; FP16-LABEL: name: test_f64.roundeven
|
|
; FP16: liveins: $d0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](f64)
|
|
; FP16-NEXT: RET_ReallyLR implicit $d0
|
|
%0:_(f64) = COPY $d0
|
|
%1:_(f64) = G_INTRINSIC_ROUNDEVEN %0
|
|
$d0 = COPY %1(f64)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: test_v8f16.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0
|
|
|
|
; NO-FP16-LABEL: name: test_v8f16.roundeven
|
|
; NO-FP16: liveins: $q0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
|
|
; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x f16>), [[UV1:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
|
|
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x f16>)
|
|
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x f16>)
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT1]]
|
|
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](<4 x f32>)
|
|
; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN1]](<4 x f32>)
|
|
; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x f16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x f16>), [[FPTRUNC1]](<4 x f16>)
|
|
; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x f16>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
|
|
;
|
|
; FP16-LABEL: name: test_v8f16.roundeven
|
|
; FP16: liveins: $q0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<8 x f16>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<8 x f16>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<8 x f16>) = COPY $q0
|
|
%1:_(<8 x f16>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$q0 = COPY %1(<8 x f16>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: test_v4f16.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
; NO-FP16-LABEL: name: test_v4f16.roundeven
|
|
; NO-FP16: liveins: $d0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
|
|
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x f16>)
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]
|
|
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](<4 x f32>)
|
|
; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x f16>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
|
|
;
|
|
; FP16-LABEL: name: test_v4f16.roundeven
|
|
; FP16: liveins: $d0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f16>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x f16>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $d0
|
|
%0:_(<4 x f16>) = COPY $d0
|
|
%1:_(<4 x f16>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$d0 = COPY %1(<4 x f16>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: test_v2f32.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
; NO-FP16-LABEL: name: test_v2f32.roundeven
|
|
; NO-FP16: liveins: $d0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f32>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
|
|
;
|
|
; FP16-LABEL: name: test_v2f32.roundeven
|
|
; FP16: liveins: $d0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f32>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $d0
|
|
%0:_(<2 x f32>) = COPY $d0
|
|
%1:_(<2 x f32>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$d0 = COPY %1(<2 x f32>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: test_v4f32.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0
|
|
|
|
; NO-FP16-LABEL: name: test_v4f32.roundeven
|
|
; NO-FP16: liveins: $q0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x f32>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
|
|
;
|
|
; FP16-LABEL: name: test_v4f32.roundeven
|
|
; FP16: liveins: $q0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x f32>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<4 x f32>) = COPY $q0
|
|
%1:_(<4 x f32>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$q0 = COPY %1(<4 x f32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: test_v2f64.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0
|
|
|
|
; NO-FP16-LABEL: name: test_v2f64.roundeven
|
|
; NO-FP16: liveins: $q0
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f64>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
|
|
;
|
|
; FP16-LABEL: name: test_v2f64.roundeven
|
|
; FP16: liveins: $q0
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f64>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<2 x f64>) = COPY $q0
|
|
%1:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$q0 = COPY %1(<2 x f64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: test_v4f64.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
|
|
; NO-FP16-LABEL: name: test_v4f64.roundeven
|
|
; NO-FP16: liveins: $q0, $q1
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
|
|
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $q1
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY1]]
|
|
; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f64>)
|
|
; NO-FP16-NEXT: $q1 = COPY [[INTRINSIC_ROUNDEVEN1]](<2 x f64>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
|
|
;
|
|
; FP16-LABEL: name: test_v4f64.roundeven
|
|
; FP16: liveins: $q0, $q1
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
|
|
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $q1
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<2 x f64>) = G_INTRINSIC_ROUNDEVEN [[COPY1]]
|
|
; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x f64>)
|
|
; FP16-NEXT: $q1 = COPY [[INTRINSIC_ROUNDEVEN1]](<2 x f64>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<2 x f64>) = COPY $q0
|
|
%1:_(<2 x f64>) = COPY $q1
|
|
%2:_(<4 x f64>) = G_CONCAT_VECTORS %0, %1
|
|
%3:_(<4 x f64>) = G_INTRINSIC_ROUNDEVEN %2
|
|
%4:_(<2 x f64>), %5:_(<2 x f64>) = G_UNMERGE_VALUES %3
|
|
$q0 = COPY %4(<2 x f64>)
|
|
$q1 = COPY %5(<2 x f64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: test_v2f16.roundeven
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1
|
|
|
|
; NO-FP16-LABEL: name: test_v2f16.roundeven
|
|
; NO-FP16: liveins: $s0, $s1
|
|
; NO-FP16-NEXT: {{ $}}
|
|
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $s0
|
|
; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<2 x f16>)
|
|
; NO-FP16-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
|
|
; NO-FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV]](f16), [[UV1]](f16), [[DEF]](f16), [[DEF]](f16)
|
|
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[BUILD_VECTOR]](<4 x f16>)
|
|
; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<2 x f32>), [[UV3:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
|
|
; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x f32>) = G_INTRINSIC_ROUNDEVEN [[UV2]]
|
|
; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[INTRINSIC_ROUNDEVEN]](<2 x f32>)
|
|
; NO-FP16-NEXT: [[DEF1:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
|
|
; NO-FP16-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[UV4]](f32), [[UV5]](f32), [[DEF1]](f32), [[DEF1]](f32)
|
|
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x f16>) = G_FPTRUNC [[BUILD_VECTOR1]](<4 x f32>)
|
|
; NO-FP16-NEXT: [[UV6:%[0-9]+]]:_(<2 x f16>), [[UV7:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[FPTRUNC]](<4 x f16>)
|
|
; NO-FP16-NEXT: $s0 = COPY [[UV6]](<2 x f16>)
|
|
; NO-FP16-NEXT: RET_ReallyLR implicit $s0
|
|
;
|
|
; FP16-LABEL: name: test_v2f16.roundeven
|
|
; FP16: liveins: $s0, $s1
|
|
; FP16-NEXT: {{ $}}
|
|
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $s0
|
|
; FP16-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<2 x f16>)
|
|
; FP16-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
|
|
; FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV]](f16), [[UV1]](f16), [[DEF]](f16), [[DEF]](f16)
|
|
; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x f16>) = G_INTRINSIC_ROUNDEVEN [[BUILD_VECTOR]]
|
|
; FP16-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[INTRINSIC_ROUNDEVEN]](<4 x f16>)
|
|
; FP16-NEXT: $s0 = COPY [[UV2]](<2 x f16>)
|
|
; FP16-NEXT: RET_ReallyLR implicit $s0
|
|
%0:_(<2 x f16>) = COPY $s0
|
|
%1:_(<2 x f16>) = G_INTRINSIC_ROUNDEVEN %0
|
|
$s0 = COPY %1(<2 x f16>)
|
|
RET_ReallyLR implicit $s0
|