derek.holloway
7502bf64a4
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305 lines
12 KiB
YAML
305 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_scalar_or_small
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body: |
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bb.0:
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liveins: $x0, $x1, $x2, $x3
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; CHECK-LABEL: name: test_scalar_or_small
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; CHECK: liveins: $x0, $x1, $x2, $x3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
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; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s8) = G_TRUNC %0
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%3:_(s8) = G_TRUNC %1
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%4:_(s8) = G_OR %2, %3
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%5:_(s64) = G_ANYEXT %4
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$x0 = COPY %5
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...
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---
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name: test_big_scalar_power_of_2
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body: |
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bb.0:
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liveins: $x0, $x1, $x2, $x3
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; We have a temporary G_MERGE_VALUES in the legalizer that gets
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; cleaned up with the G_UNMERGE_VALUES, so we end up directly
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; copying the results of the G_OR ops.
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; CHECK-LABEL: name: test_big_scalar_power_of_2
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; CHECK: liveins: $x0, $x1, $x2, $x3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY2]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[COPY3]]
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; CHECK-NEXT: $x0 = COPY [[OR]](s64)
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; CHECK-NEXT: $x1 = COPY [[OR1]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = COPY $x2
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%3:_(s64) = COPY $x3
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%4:_(s128) = G_MERGE_VALUES %0, %1
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%5:_(s128) = G_MERGE_VALUES %2, %3
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%6:_(s128) = G_OR %4, %5
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%7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
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$x0 = COPY %7
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$x1 = COPY %8
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RET_ReallyLR implicit $x0, implicit $x1
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...
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---
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name: test_s318_or
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_s318_or
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: %ptr:_(p0) = COPY $x0
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[OR]], [[C]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[OR1]], [[C]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[OR2]], [[C]]
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[OR3]], [[C]]
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; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[OR4]], [[C1]]
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; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64), align 64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
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; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
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; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
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; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
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; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
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; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%a:_(s318) = G_IMPLICIT_DEF
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%b:_(s318) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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%or:_(s318) = G_OR %a, %b
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G_STORE %or(s318), %ptr(p0) :: (store (s318))
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RET_ReallyLR implicit $x0
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...
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---
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name: test_vector_or_v16s16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_vector_or_v16s16
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY]], [[COPY]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY1]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[OR]](<8 x s16>)
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; CHECK-NEXT: $q1 = COPY [[OR1]](<8 x s16>)
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%1:_(<8 x s16>) = COPY $q0
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%2:_(<8 x s16>) = COPY $q1
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%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
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%3:_(<16 x s16>) = G_OR %0, %0
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%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
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$q0 = COPY %4(<8 x s16>)
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$q1 = COPY %5(<8 x s16>)
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...
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---
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name: test_vector_or_v32s8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_vector_or_v32s8
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY]]
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY1]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
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; CHECK-NEXT: $q1 = COPY [[OR1]](<16 x s8>)
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%0:_(<16 x s8>) = COPY $q0
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%1:_(<16 x s8>) = COPY $q1
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%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
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%3:_(<32 x s8>) = G_OR %2, %2
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%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
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$q0 = COPY %7(<16 x s8>)
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$q1 = COPY %8(<16 x s8>)
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...
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---
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name: or_v2s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $d2, $d3
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; CHECK-LABEL: name: or_v2s1
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; CHECK: liveins: $d0, $d1, $d2, $d3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: $d0 = COPY [[OR]](<2 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = COPY $d2
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%3:_(<2 x s32>) = COPY $d3
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%4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
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%5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
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%6:_(<2 x s1>) = G_OR %4, %5
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%7:_(<2 x s32>) = G_ANYEXT %6
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$d0 = COPY %7:_(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: or_v3s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $b0, $b1, $b2
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; CHECK-LABEL: name: or_v3s1
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; CHECK: liveins: $b0, $b1, $b2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
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; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
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; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
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; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
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; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
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; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT3]](s16), [[ANYEXT4]](s16), [[ANYEXT5]](s16), [[DEF]](s16)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR]](<4 x s16>)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
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; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
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; CHECK-NEXT: RET_ReallyLR implicit $b0
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%1:_(s8) = COPY $b0
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%2:_(s8) = COPY $b1
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%3:_(s8) = COPY $b2
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%4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
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%0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
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%5:_(<3 x s1>) = G_OR %0, %0
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%7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
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%8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
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$b0 = COPY %8:_(s8)
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RET_ReallyLR implicit $b0
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...
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---
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name: or_v4s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $d2, $d3
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; CHECK-LABEL: name: or_v4s1
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; CHECK: liveins: $d0, $d1, $d2, $d3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: $d0 = COPY [[OR]](<4 x s16>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = COPY $d1
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%2:_(<4 x s16>) = COPY $d2
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%3:_(<4 x s16>) = COPY $d3
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%4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
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%5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
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%6:_(<4 x s1>) = G_OR %4, %5
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%7:_(<4 x s16>) = G_ANYEXT %6
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$d0 = COPY %7:_(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: or_v8s1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $d2, $d3
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; CHECK-LABEL: name: or_v8s1
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; CHECK: liveins: $d0, $d1, $d2, $d3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s8>) = G_OR [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: $d0 = COPY [[OR]](<8 x s8>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s8>) = COPY $d2
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%3:_(<8 x s8>) = COPY $d3
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%4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
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%5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
|
|
%6:_(<8 x s1>) = G_OR %4, %5
|
|
%7:_(<8 x s8>) = G_ANYEXT %6
|
|
$d0 = COPY %7:_(<8 x s8>)
|
|
RET_ReallyLR implicit $d0
|
|
...
|
|
---
|
|
name: or_v16s1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $q0, $q1, $q2, $q3
|
|
|
|
; CHECK-LABEL: name: or_v16s1
|
|
; CHECK: liveins: $q0, $q1, $q2, $q3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
|
|
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
|
|
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
|
|
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[ICMP]], [[ICMP1]]
|
|
; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:_(<16 x s8>) = COPY $q0
|
|
%1:_(<16 x s8>) = COPY $q1
|
|
%2:_(<16 x s8>) = COPY $q2
|
|
%3:_(<16 x s8>) = COPY $q3
|
|
%4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
|
|
%5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
|
|
%6:_(<16 x s1>) = G_OR %4, %5
|
|
%7:_(<16 x s8>) = G_ANYEXT %6
|
|
$q0 = COPY %7:_(<16 x s8>)
|
|
RET_ReallyLR implicit $q0
|
|
...
|