derek.holloway
7502bf64a4
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182 lines
6.9 KiB
YAML
182 lines
6.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: add_v16s8
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v16s8
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
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%2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
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%3:_(s32) = G_ANYEXT %2(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v8s16
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v8s16
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
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%2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
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%3:_(s32) = G_ANYEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v4s32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v4s32
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
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; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
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%2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v2s64
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v2s64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
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; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%1:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
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%2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: add_v2s32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v2s32
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
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; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
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%2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_v8i64
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# This is a power-of-2 legalization, so use a tree reduction.
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1, $q2, $q3
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; CHECK-LABEL: name: test_v8i64
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; CHECK: liveins: $q0, $q1, $q2, $q3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
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; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = COPY $q1
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%2:_(<2 x s64>) = COPY $q2
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%3:_(<2 x s64>) = COPY $q3
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%4:_(<4 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>)
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%5:_(<4 x s64>) = G_CONCAT_VECTORS %2(<2 x s64>), %3(<2 x s64>)
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%6:_(<8 x s64>) = G_CONCAT_VECTORS %4(<4 x s64>), %5(<4 x s64>)
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%7:_(s64) = G_VECREDUCE_ADD %6(<8 x s64>)
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$x0 = COPY %7(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: test_v6i64
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# This is a non-power-of-2 legalization, generate multiple vector reductions
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# and combine them with scalar ops.
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1, $q2, $q3
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; CHECK-LABEL: name: test_v6i64
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; CHECK: liveins: $q0, $q1, $q2, $q3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C1]](i64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C2]](i64)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[IVEC1]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
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; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
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; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = COPY $q1
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%2:_(<2 x s64>) = COPY $q2
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%3:_(<6 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>), %2(<2 x s64>)
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%4:_(s64) = G_VECREDUCE_ADD %3(<6 x s64>)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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