derek.holloway
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94 lines
3.3 KiB
YAML
94 lines
3.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: fmin_v2s32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0
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; CHECK-LABEL: name: fmin_v2s32
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
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; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(f32) = G_VECREDUCE_FMIN [[COPY]](<2 x f32>)
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; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](f32)
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:_(<2 x f32>) = COPY $d0
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%1:_(f32) = G_VECREDUCE_FMIN %0(<2 x f32>)
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$s0 = COPY %1(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fmax_v8s16
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: fmax_v8s16
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x f16>), [[UV1:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
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; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x f16>)
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; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x f16>)
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; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<4 x f32>) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
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; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAX [[FMAXNUM]](<4 x f32>)
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; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[VECREDUCE_FMAX]](f32)
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; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:_(<8 x f16>) = COPY $q0
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%1:_(f16) = G_VECREDUCE_FMAX %0(<8 x f16>)
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$h0 = COPY %1(f16)
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RET_ReallyLR implicit $h0
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...
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---
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name: fminimum_v2s32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0
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; CHECK-LABEL: name: fminimum_v2s32
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
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; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMINIMUM [[COPY]](<2 x f32>)
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; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](f32)
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:_(<2 x f32>) = COPY $d0
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%1:_(f32) = G_VECREDUCE_FMINIMUM %0(<2 x f32>)
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$s0 = COPY %1(f32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fmaximum_v8s16
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: fmaximum_v8s16
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x f16>), [[UV1:%[0-9]+]]:_(<4 x f16>) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
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; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x f16>)
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; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x f16>)
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; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<4 x f32>) = G_FMAXIMUM [[FPEXT]], [[FPEXT1]]
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; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAXIMUM [[FMAXIMUM]](<4 x f32>)
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; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[VECREDUCE_FMAXIMUM]](f32)
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; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:_(<8 x f16>) = COPY $q0
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%1:_(f16) = G_VECREDUCE_FMAXIMUM %0(<8 x f16>)
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$h0 = COPY %1(f16)
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RET_ReallyLR implicit $h0
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...
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