derek.holloway
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161 lines
5.9 KiB
YAML
161 lines
5.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: rotr_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: rotr_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](s32)
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; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](i64)
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; CHECK-NEXT: $w0 = COPY %rot(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%rot:_(s32) = G_ROTR %0(s32), %1(s32)
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$w0 = COPY %rot(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotr_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: rotr_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: %rot:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
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; CHECK-NEXT: $x0 = COPY %rot(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%rot:_(s64) = G_ROTR %0(s64), %1(s64)
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$x0 = COPY %rot(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: rotl_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: rotl_s32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[SUB]](s32)
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; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](i64)
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; CHECK-NEXT: $w0 = COPY %rot(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%rot:_(s32) = G_ROTL %0(s32), %1(s32)
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$w0 = COPY %rot(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotl_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: rotl_s64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: %rot:_(s64) = G_ROTR [[COPY]], [[SUB]](s64)
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; CHECK-NEXT: $x0 = COPY %rot(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%rot:_(s64) = G_ROTL %0(s64), %1(s64)
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$x0 = COPY %rot(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: test_rotl_v4s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_rotl_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND]](<4 x s32>)
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND1]](<4 x s32>)
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; CHECK-NEXT: %rot:_(<4 x s32>) = disjoint G_OR [[SHL]], [[LSHR]]
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; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%rot:_(<4 x s32>) = G_ROTL %0(<4 x s32>), %1(<4 x s32>)
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$q0 = COPY %rot(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_rotr_v4s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_rotr_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND]](<4 x s32>)
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND1]](<4 x s32>)
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; CHECK-NEXT: %rot:_(<4 x s32>) = disjoint G_OR [[LSHR]], [[SHL]]
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; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%rot:_(<4 x s32>) = G_ROTR %0(<4 x s32>), %1(<4 x s32>)
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$q0 = COPY %rot(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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