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96 lines
4.1 KiB
YAML
96 lines
4.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-apple-ios"
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define void @udiv_test(ptr %v1ptr, ptr %v2ptr) { ret void }
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define void @sdiv_test(ptr %v1ptr, ptr %v2ptr) { ret void }
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...
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---
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name: udiv_test
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: udiv_test
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
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; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
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; CHECK-NEXT: $x0 = COPY [[UV]](i64)
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; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
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; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
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; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
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; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
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; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)
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%3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)
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%4:_(s128) = G_UDIV %2, %3
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G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)
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RET_ReallyLR
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...
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---
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name: sdiv_test
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: sdiv_test
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
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; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
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; CHECK-NEXT: $x0 = COPY [[UV]](i64)
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; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
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; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
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; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
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; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
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; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
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; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
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; CHECK-NEXT: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)
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%3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)
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%4:_(s128) = G_SDIV %2, %3
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G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)
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RET_ReallyLR
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...
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