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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
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derek.holloway 7502bf64a4
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
---
name: narrow_sext_s128
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: narrow_sext_s128
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[COPY]], [[C]](i64)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store (s128))
; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s128) = G_SEXT %0(s64)
G_STORE %2(s128), %1(p0) :: (store (s128))
RET_ReallyLR
...
---
name: narrow_zext_s128
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: narrow_zext_s128
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store (s128))
; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s128) = G_ZEXT %0(s64)
G_STORE %2(s128), %1(p0) :: (store (s128))
RET_ReallyLR
...
---
name: narrow_zext_s128_from_s32
tracksRegLiveness: true
body: |
bb.1:
liveins: $w0, $x1
; CHECK-LABEL: name: narrow_zext_s128_from_s32
; CHECK: liveins: $w0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64)
; CHECK-NEXT: G_STORE [[MV1]](s128), [[COPY1]](p0) :: (store (s128))
; CHECK-NEXT: RET_ReallyLR
%0:_(s32) = COPY $w0
%1:_(p0) = COPY $x1
%2:_(s128) = G_ZEXT %0(s32)
G_STORE %2(s128), %1(p0) :: (store (s128))
RET_ReallyLR
...
---
name: narrow_zext_s192
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: narrow_zext_s192
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64))
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY1]](p0) :: (store (s64))
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY1]](p0) :: (store (s64))
; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s192) = G_ZEXT %0(s64)
%3:_(s64), %4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %2(s192)
G_STORE %3, %1(p0) :: (store (s64))
G_STORE %4, %1(p0) :: (store (s64))
G_STORE %5, %1(p0) :: (store (s64))
RET_ReallyLR
...