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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
# RUN: | FileCheck %s
...
---
name: test_v4f16.sin
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v4f16.sin
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY1]](f32)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT1]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY2]](f32)
; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT2]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY3]](f32)
; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT3]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY4]](f32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16), [[FPTRUNC2]](f16), [[FPTRUNC3]](f16)
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x f16>) = COPY $d0
%1:_(<4 x f16>) = G_FSIN %0
$d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.sin
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8f16.sin
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16), [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16), [[UV6:%[0-9]+]]:_(f16), [[UV7:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<8 x f16>)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY1]](f32)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT1]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY2]](f32)
; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT2]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY3]](f32)
; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT3]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY4]](f32)
; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[UV4]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT4]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY5]](f32)
; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[UV5]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT5]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY6]](f32)
; CHECK-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[UV6]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT6]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY7]](f32)
; CHECK-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[UV7]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT7]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY8]](f32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x f16>) = G_BUILD_VECTOR [[FPTRUNC]](f16), [[FPTRUNC1]](f16), [[FPTRUNC2]](f16), [[FPTRUNC3]](f16), [[FPTRUNC4]](f16), [[FPTRUNC5]](f16), [[FPTRUNC6]](f16), [[FPTRUNC7]](f16)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<8 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x f16>) = COPY $q0
%1:_(<8 x f16>) = G_FSIN %0
$q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f32.sin
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v2f32.sin
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV1]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32)
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x f32>) = COPY $d0
%1:_(<2 x f32>) = G_FSIN %0
$d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.sin
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v4f32.sin
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV1]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV2]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[UV3]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32), [[COPY3]](f32), [[COPY4]](f32)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x f32>) = COPY $q0
%1:_(<4 x f32>) = G_FSIN %0
$q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.sin
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v2f64.sin
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $d0 = COPY [[UV]](f64)
; CHECK-NEXT: BL &sin, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $d0 = COPY [[UV1]](f64)
; CHECK-NEXT: BL &sin, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $d0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[COPY1]](f64), [[COPY2]](f64)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x f64>) = COPY $q0
%1:_(<2 x f64>) = G_FSIN %0
$q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
...
---
name: test_sin_half
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: test_sin_half
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[COPY]](f16)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: BL &sinf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY1]](f32)
; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:_(f16) = COPY $h0
%1:_(f16) = G_FSIN %0
$h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
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