derek.holloway
7502bf64a4
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180 lines
8.4 KiB
YAML
180 lines
8.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: smulfix_i32_scale_0
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: smulfix_i32_scale_0
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = G_MUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[MUL]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(i32) = COPY $w0
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%1:_(i32) = COPY $w1
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%2:_(i32) = G_UMULFIX %0, %1, 0
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$w0 = COPY %2(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: smulfix_i32
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body: |
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bb.1:
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liveins: $w0, $w1
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; CHECK-LABEL: name: smulfix_i32
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](i32)
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[ZEXT1]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[MUL]], [[C]](i64)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
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; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(i32) = COPY $w0
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%1:_(i32) = COPY $w1
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%2:_(i32) = G_UMULFIX %0, %1, 15
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$w0 = COPY %2(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: smulfix_i64
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body: |
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bb.1:
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liveins: $x0, $x1
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; CHECK-LABEL: name: smulfix_i64
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(i64) = G_UMULH [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[COPY]], [[C1]]
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; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(i64) = G_MUL [[C1]], [[COPY1]]
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[UMULH]], [[MUL1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i64) = G_ADD [[ADD]], [[MUL2]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[MUL]], [[C]](i64)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 49
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ADD1]], [[C2]](i64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(i64) = G_OR [[LSHR]], [[SHL]]
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; CHECK-NEXT: $x0 = COPY [[OR]](i64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:_(i64) = COPY $x0
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%1:_(i64) = COPY $x1
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%2:_(i64) = G_UMULFIX %0, %1, 15
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$x0 = COPY %2(i64)
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RET_ReallyLR implicit $x0
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...
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---
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name: smulfix_4xi32
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulfix_4xi32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i32>), [[UV1:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV1]](<2 x i32>)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x i32>), [[UV3:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY1]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV2]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV3]](<2 x i32>)
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT]], [[ZEXT2]]
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; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT1]], [[ZEXT3]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL1]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR1]](<2 x i64>)
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; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x i32>), [[TRUNC1]](<2 x i32>)
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; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<4 x i32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x i32>) = COPY $q0
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%1:_(<4 x i32>) = COPY $q1
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%2:_(<4 x i32>) = G_UMULFIX %0, %1, 2
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$q0 = COPY %2(<4 x i32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: smulfix_4xi32_15
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulfix_4xi32_15
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i32>), [[UV1:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV1]](<2 x i32>)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x i32>), [[UV3:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY1]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV2]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV3]](<2 x i32>)
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT]], [[ZEXT2]]
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; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT1]], [[ZEXT3]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL1]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR1]](<2 x i64>)
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; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x i32>), [[TRUNC1]](<2 x i32>)
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; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<4 x i32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x i32>) = COPY $q0
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%1:_(<4 x i32>) = COPY $q1
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%2:_(<4 x i32>) = G_UMULFIX %0, %1, 15
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$q0 = COPY %2(<4 x i32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: smulfix_4xi32_31
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: smulfix_4xi32_31
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 31
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i32>), [[UV1:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV1]](<2 x i32>)
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; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x i32>), [[UV3:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY1]](<4 x i32>)
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV2]](<2 x i32>)
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; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[UV3]](<2 x i32>)
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT]], [[ZEXT2]]
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; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<2 x i64>) = G_MUL [[ZEXT1]], [[ZEXT3]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<2 x i64>) = G_LSHR [[MUL1]], [[BUILD_VECTOR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR]](<2 x i64>)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<2 x i32>) = G_TRUNC [[LSHR1]](<2 x i64>)
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; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i32>) = G_CONCAT_VECTORS [[TRUNC]](<2 x i32>), [[TRUNC1]](<2 x i32>)
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; CHECK-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<4 x i32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x i32>) = COPY $q0
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%1:_(<4 x i32>) = COPY $q1
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%2:_(<4 x i32>) = G_UMULFIX %0, %1, 31
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$q0 = COPY %2(<4 x i32>)
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RET_ReallyLR implicit $q0
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...
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