derek.holloway
7502bf64a4
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481 lines
14 KiB
YAML
481 lines
14 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: shl_gep_sext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with two 1s, representing a shift
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; plus sign extend.
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; CHECK-LABEL: name: shl_gep_sext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 1, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 2
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%offset:gpr(i64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_gep_zext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with a 0 representing a zero-extend
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; and a 1 representing a shift.
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; CHECK-LABEL: name: shl_gep_zext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_ZEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 2
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%offset:gpr(i64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_gep_anyext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with a 0 representing a zero-extend
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; and a 1 representing a shift.
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; CHECK-LABEL: name: shl_gep_anyext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_ANYEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 2
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%offset:gpr(i64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_sext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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; We should be able to do the same with multiplies as with shifts.
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liveins: $w1, $x0
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; CHECK-LABEL: name: mul_gep_sext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 1, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 4
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_zext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to do the same with multiplies as with shifts.
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; CHECK-LABEL: name: mul_gep_zext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_ZEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 4
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_anyext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to do the same with multiplies as with shifts.
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; CHECK-LABEL: name: mul_gep_anyext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load (s32))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_ANYEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 4
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ldrdrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0, $d0
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; Verify that we can select LDRDroW.
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; CHECK-LABEL: name: ldrdrow
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; CHECK: liveins: $w1, $x0, $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:fpr64 = LDRDroW %base, %foo, 1, 1 :: (load (<2 x s32>))
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; CHECK-NEXT: $x0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 8
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:fpr(<2 x s32>) = G_LOAD %ptr(p0) :: (load (<2 x s32>))
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$x0 = COPY %load(<2 x s32>)
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RET_ReallyLR implicit $x0
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...
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---
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name: ldrxrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0, $d0
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; Verify that we can select LDRXroW.
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; CHECK-LABEL: name: ldrxrow
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; CHECK: liveins: $w1, $x0, $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:gpr64 = LDRXroW %base, %foo, 1, 1 :: (load (s64))
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; CHECK-NEXT: $x0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 8
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
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$x0 = COPY %load(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: ldrbbrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $x0, $w0, $w1
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; Verify that we can select LDRBBroW. Note that there is no shift here,
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; but we still fold the extend into the addressing mode.
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; CHECK-LABEL: name: ldrbbrow
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; CHECK: liveins: $x0, $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:gpr32 = COPY $w1
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %load:gpr32 = LDRBBroW %base, %val, 1, 0 :: (load (s8))
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; CHECK-NEXT: $w0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%val:gpr(i32) = COPY $w1
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%base:gpr(p0) = COPY $x0
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%ext:gpr(i64) = G_SEXT %val(i32)
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%ptr:gpr(p0) = G_PTR_ADD %base, %ext(i64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s8))
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ldrhrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $w1, $x0
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; Verify that we can select ldrhrow.
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; CHECK-LABEL: name: ldrhrow
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; CHECK: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %foo:gpr32 = COPY $w1
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; CHECK-NEXT: %load:fpr16 = LDRHroW %base, %foo, 1, 1 :: (load (s16))
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; CHECK-NEXT: $h0 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %foo(i32)
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%c:gpr(i64) = G_CONSTANT i64 2
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%offset:gpr(i64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
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%load:fpr(s16) = G_LOAD %ptr(p0) :: (load (s16))
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$h0 = COPY %load(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: bad_and_mask_1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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bb.0:
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liveins: $x0
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; We should get a roX load here, not a roW load. We can't use the mask in
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; this test for an extend.
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; CHECK-LABEL: name: bad_and_mask_1
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %base:gpr64sp = COPY $x0
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; CHECK-NEXT: %imp:gpr64 = IMPLICIT_DEF
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; CHECK-NEXT: %and:gpr64common = ANDXri %imp, 4103
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; CHECK-NEXT: %load:gpr64 = LDRXroX %base, %and, 0, 1 :: (load (s64))
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; CHECK-NEXT: $x1 = COPY %load
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; CHECK-NEXT: RET_ReallyLR implicit $x1
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%base:gpr(p0) = COPY $x0
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%imp:gpr(i64) = G_IMPLICIT_DEF
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%bad_mask:gpr(i64) = G_CONSTANT i64 255
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%and:gpr(i64) = G_AND %imp, %bad_mask
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%c:gpr(i64) = G_CONSTANT i64 8
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%mul:gpr(i64) = G_MUL %c, %and
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%ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
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$x1 = COPY %load(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: bad_and_mask_2
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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bb.0:
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liveins: $x0
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; We should get a roX load here, not a roW load. We can't use the mask in
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; this test for an extend.
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; CHECK-LABEL: name: bad_and_mask_2
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %base:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: %imp:gpr64 = IMPLICIT_DEF
|
|
; CHECK-NEXT: %and:gpr64common = ANDXri %imp, 4111
|
|
; CHECK-NEXT: %load:gpr64 = LDRXroX %base, %and, 0, 1 :: (load (s64))
|
|
; CHECK-NEXT: $x1 = COPY %load
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x1
|
|
%base:gpr(p0) = COPY $x0
|
|
%imp:gpr(i64) = G_IMPLICIT_DEF
|
|
%bad_mask:gpr(i64) = G_CONSTANT i64 65535
|
|
%and:gpr(i64) = G_AND %imp, %bad_mask
|
|
%c:gpr(i64) = G_CONSTANT i64 8
|
|
%mul:gpr(i64) = G_MUL %c, %and
|
|
%ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
|
|
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
|
|
$x1 = COPY %load(s64)
|
|
RET_ReallyLR implicit $x1
|
|
...
|
|
---
|
|
name: and_uxtw
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
|
|
; The mask used for the AND here is legal for producing a roW load.
|
|
|
|
; CHECK-LABEL: name: and_uxtw
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %base:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: %imp:gpr64 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %imp.sub_32
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
|
|
; CHECK-NEXT: %load:gpr64 = LDRXroW %base, [[COPY1]], 0, 1 :: (load (s64))
|
|
; CHECK-NEXT: $x1 = COPY %load
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x1
|
|
%base:gpr(p0) = COPY $x0
|
|
%imp:gpr(i64) = G_IMPLICIT_DEF
|
|
%mask:gpr(i64) = G_CONSTANT i64 4294967295
|
|
%and:gpr(i64) = G_AND %imp, %mask
|
|
%c:gpr(i64) = G_CONSTANT i64 8
|
|
%mul:gpr(i64) = G_MUL %c, %and
|
|
%ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
|
|
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
|
|
$x1 = COPY %load(s64)
|
|
RET_ReallyLR implicit $x1
|
|
...
|
|
---
|
|
name: zext_shl_LDRWroW
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$w0' }
|
|
- { reg: '$x1' }
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0, $x1
|
|
|
|
; We try to look through the G_ZEXT of the SHL here.
|
|
|
|
; CHECK-LABEL: name: zext_shl_LDRWroW
|
|
; CHECK: liveins: $w0, $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
|
|
; CHECK-NEXT: [[ANDWri:%[0-9]+]]:gpr32common = ANDWri [[COPY]], 7
|
|
; CHECK-NEXT: [[LDRWroW:%[0-9]+]]:gpr32 = LDRWroW [[COPY1]], [[ANDWri]], 0, 1 :: (load (s32))
|
|
; CHECK-NEXT: $w0 = COPY [[LDRWroW]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(p0) = COPY $x1
|
|
%2:gpr(i32) = G_CONSTANT i32 255
|
|
%3:gpr(i32) = G_AND %0, %2
|
|
%13:gpr(i64) = G_CONSTANT i64 2
|
|
%12:gpr(i32) = G_SHL %3, %13(i64)
|
|
%6:gpr(i64) = G_ZEXT %12(i32)
|
|
%7:gpr(p0) = G_PTR_ADD %1, %6(i64)
|
|
%9:gpr(s32) = G_LOAD %7(p0) :: (load (s32))
|
|
$w0 = COPY %9(s32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|