derek.holloway
7502bf64a4
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267 lines
7.3 KiB
YAML
267 lines
7.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify that we can fold G_AND into G_BRCOND when all of the following hold:
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# 1. We have a ne/eq G_ICMP feeding into the G_BRCOND
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# 2. The G_ICMP is being compared against 0
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# 3. One of the operands of the G_AND is a power of 2
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#
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# If all of these hold, we should produce a tbnz or a tbz.
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...
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---
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name: tbnzx_and
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbnzx_and
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: TBNZX [[COPY]], 33, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
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%3:gpr(i64) = G_CONSTANT i64 0
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%2:gpr(i64) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbzx_and
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: tbzx_and
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: TBZX [[COPY]], 33, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
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%3:gpr(i64) = G_CONSTANT i64 0
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%2:gpr(i64) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(eq), %2(i64), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbnzw_and
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: tbnzw_and
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: TBNZW [[COPY]], 0, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = G_CONSTANT i32 1
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%3:gpr(i32) = G_CONSTANT i32 0
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%2:gpr(i32) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(ne), %2(i32), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbzw_and
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: tbzw_and
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: TBZW [[COPY]], 0, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = G_CONSTANT i32 1
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%3:gpr(i32) = G_CONSTANT i32 0
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%2:gpr(i32) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(eq), %2(i32), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_and_lt
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_fold_and_lt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = G_CONSTANT i32 1
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%3:gpr(i32) = G_CONSTANT i32 0
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%2:gpr(i32) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(slt), %2(i32), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_and_gt
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_fold_and_gt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = G_CONSTANT i32 1
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%3:gpr(i32) = G_CONSTANT i32 0
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%2:gpr(i32) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(sgt), %2(i32), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_and_not_power_of_2
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_fold_and_not_power_of_2
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[COPY]], 4098
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; CHECK-NEXT: CBNZX [[ANDXri]], %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 7
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%3:gpr(i64) = G_CONSTANT i64 0
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%2:gpr(i64) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_cmp_not_0
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_fold_cmp_not_0
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064
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; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 4
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%3:gpr(i64) = G_CONSTANT i64 4
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%2:gpr(i64) = G_AND %0, %1
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%5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
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G_BRCOND %5, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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