TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
#
# Check that we can continue matching when we are in a situation where we will
# emit a TB(N)Z.
...
---
name:            fold_zext
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: fold_zext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
  ; CHECK-NEXT:   TBNZW %copy, 3, %bb.1
  ; CHECK-NEXT:   B %bb.0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.0:
    successors: %bb.0, %bb.1
    liveins: $x0
    %copy:gpr(s32) = COPY $w0
    %bit:gpr(s64) = G_CONSTANT i64 8
    %zero:gpr(s64) = G_CONSTANT i64 0
    %fold_me:gpr(s64) = G_ZEXT %copy(s32)
    %and:gpr(s64) = G_AND %fold_me, %bit
    %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
    G_BRCOND %cmp, %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR
...
---
name:            fold_anyext
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: fold_anyext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
  ; CHECK-NEXT:   TBNZW %copy, 3, %bb.1
  ; CHECK-NEXT:   B %bb.0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.0:
    successors: %bb.0, %bb.1
    liveins: $x0
    %copy:gpr(s32) = COPY $w0
    %bit:gpr(s64) = G_CONSTANT i64 8
    %zero:gpr(s64) = G_CONSTANT i64 0
    %fold_me:gpr(s64) = G_ANYEXT %copy(s32)
    %and:gpr(s64) = G_AND %fold_me, %bit
    %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
    G_BRCOND %cmp, %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR
...
---
name:            fold_multiple
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: fold_multiple
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $h0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub
  ; CHECK-NEXT:   %copy:gpr32all = COPY [[SUBREG_TO_REG]]
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY %copy
  ; CHECK-NEXT:   TBNZW [[COPY]], 3, %bb.1
  ; CHECK-NEXT:   B %bb.0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.0:
    successors: %bb.0, %bb.1
    liveins: $h0
    %copy:gpr(s16) = COPY $h0
    %bit:gpr(s64) = G_CONSTANT i64 8
    %zero:gpr(s64) = G_CONSTANT i64 0
    %ext1:gpr(s32) = G_ZEXT %copy(s16)
    %ext2:gpr(s64) = G_ANYEXT %ext1(s32)
    %and:gpr(s64) = G_AND %ext2, %bit
    %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
    G_BRCOND %cmp, %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR
...
---
name:            dont_fold_more_than_one_use
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: dont_fold_more_than_one_use
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $x0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
  ; CHECK-NEXT:   %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
  ; CHECK-NEXT:   TBNZW [[COPY1]], 3, %bb.1
  ; CHECK-NEXT:   B %bb.0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   $x0 = COPY %zext
  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
  bb.0:
    successors: %bb.0, %bb.1
    liveins: $x0
    %copy:gpr(s32) = COPY $w0
    %bit:gpr(s64) = G_CONSTANT i64 8
    %zero:gpr(s64) = G_CONSTANT i64 0
    %zext:gpr(s64) = G_ZEXT %copy(s32)
    %and:gpr(s64) = G_AND %zext, %bit
    %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
    G_BRCOND %cmp, %bb.1
    G_BR %bb.0
  bb.1:
    $x0 = COPY %zext:gpr(s64)
    RET_ReallyLR implicit $x0