derek.holloway
7502bf64a4
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199 lines
7.2 KiB
YAML
199 lines
7.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=LOWER
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# RUN: llc -mtriple aarch64 -O2 -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECT
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...
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---
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name: same_reg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; LOWER-LABEL: name: same_reg
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; LOWER: liveins: $d0
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<8 x i8>) = G_IMPLICIT_DEF
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; LOWER-NEXT: %build_vector:_(<8 x i8>) = COPY [[DEF]](<8 x i8>)
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; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: same_reg
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; SELECT: liveins: $d0
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
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; SELECT-NEXT: $d0 = COPY [[DEF]]
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%r:_(i8) = G_IMPLICIT_DEF
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%build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
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$d0 = COPY %build_vector(<8 x i8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: dont_combine_different_reg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0, $w1
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; LOWER-LABEL: name: dont_combine_different_reg
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; LOWER: liveins: $d0, $w0, $w1
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: %r:_(i32) = COPY $w0
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; LOWER-NEXT: %q:_(i32) = COPY $w1
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; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
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; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(i32), [[C]](i64)
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; LOWER-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
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; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(i32), [[C1]](i64)
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; LOWER-NEXT: %build_vector:_(<2 x i32>) = COPY [[IVEC1]](<2 x i32>)
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; LOWER-NEXT: $d0 = COPY %build_vector(<2 x i32>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: dont_combine_different_reg
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; SELECT: liveins: $d0, $w0, $w1
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: %r:gpr32 = COPY $w0
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; SELECT-NEXT: %q:gpr32 = COPY $w1
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; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
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; SELECT-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr64 = INSERT_SUBREG [[DEF]], %r, %subreg.ssub
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; SELECT-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; SELECT-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[INSERT_SUBREG]], %subreg.dsub
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; SELECT-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, %q
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; SELECT-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
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; SELECT-NEXT: $d0 = COPY [[COPY]]
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%r:_(i32) = COPY $w0
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%q:_(i32) = COPY $w1
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%build_vector:_(<2 x i32>) = G_BUILD_VECTOR %r, %q
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$d0 = COPY %build_vector(<2 x i32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: dont_combine_zero
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; LOWER-LABEL: name: dont_combine_zero
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; LOWER: liveins: $d0
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: %r:_(i8) = G_CONSTANT i8 0
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; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8)
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; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: dont_combine_zero
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; SELECT: liveins: $d0
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
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; SELECT-NEXT: %build_vector:fpr64 = COPY [[MOVIv2d_ns]].dsub
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; SELECT-NEXT: $d0 = COPY %build_vector
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%r:_(i8) = G_CONSTANT i8 0
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%build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
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$d0 = COPY %build_vector(<8 x i8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: dont_combine_all_ones
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; LOWER-LABEL: name: dont_combine_all_ones
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; LOWER: liveins: $d0
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: %r:_(i8) = G_CONSTANT i8 -1
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; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8)
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; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: dont_combine_all_ones
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; SELECT: liveins: $d0
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: %build_vector:fpr64 = MOVID 255
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; SELECT-NEXT: $d0 = COPY %build_vector
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%r:_(i8) = G_CONSTANT i8 -1
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%build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
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$d0 = COPY %build_vector(<8 x i8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: all_zeros_pat_example
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; LOWER-LABEL: name: all_zeros_pat_example
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; LOWER: liveins: $d0
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: %v:_(<2 x i32>) = COPY $d0
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; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 0
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; LOWER-NEXT: %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst(i32), %cst(i32)
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; LOWER-NEXT: %sub:_(<2 x i32>) = G_SUB %build_vector, %v
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; LOWER-NEXT: $d0 = COPY %sub(<2 x i32>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: all_zeros_pat_example
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; SELECT: liveins: $d0
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: %v:fpr64 = COPY $d0
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; SELECT-NEXT: %sub:fpr64 = NEGv2i32 %v
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; SELECT-NEXT: $d0 = COPY %sub
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%v:_(<2 x i32>) = COPY $d0
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%cst:_(i32) = G_CONSTANT i32 0
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%build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst, %cst
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%sub:_(<2 x i32>) = G_SUB %build_vector, %v
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$d0 = COPY %sub(<2 x i32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: all_ones_pat_example
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; LOWER-LABEL: name: all_ones_pat_example
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; LOWER: liveins: $d0, $d1
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; LOWER-NEXT: {{ $}}
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; LOWER-NEXT: %v0:_(<2 x i32>) = COPY $d0
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; LOWER-NEXT: %v1:_(<2 x i32>) = COPY $d1
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; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 -1
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; LOWER-NEXT: %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst(i32), %cst(i32)
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; LOWER-NEXT: %xor:_(<2 x i32>) = G_XOR %v0, %build_vector
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; LOWER-NEXT: %and:_(<2 x i32>) = G_AND %v1, %xor
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; LOWER-NEXT: $d0 = COPY %and(<2 x i32>)
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; LOWER-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECT-LABEL: name: all_ones_pat_example
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; SELECT: liveins: $d0, $d1
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; SELECT-NEXT: {{ $}}
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; SELECT-NEXT: %v0:fpr64 = COPY $d0
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; SELECT-NEXT: %v1:fpr64 = COPY $d1
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; SELECT-NEXT: %and:fpr64 = BICv8i8 %v1, %v0
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; SELECT-NEXT: $d0 = COPY %and
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; SELECT-NEXT: RET_ReallyLR implicit $d0
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%v0:_(<2 x i32>) = COPY $d0
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%v1:_(<2 x i32>) = COPY $d1
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%cst:_(i32) = G_CONSTANT i32 -1
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%build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst, %cst
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%xor:_(<2 x i32>) = G_XOR %v0, %build_vector
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%and:_(<2 x i32>) = G_AND %v1, %xor
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$d0 = COPY %and(<2 x i32>)
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RET_ReallyLR implicit $d0
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