derek.holloway
7502bf64a4
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177 lines
6.3 KiB
YAML
177 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=aarch64 -global-isel -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECTED
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---
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name: duplane64
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: duplane64
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](i64)
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; CHECK-NEXT: $q0 = COPY [[DUPLANE64_]](<2 x s64>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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;
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; SELECTED-LABEL: name: duplane64
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; SELECTED: liveins: $q0
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; SELECTED-NEXT: {{ $}}
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; SELECTED-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; SELECTED-NEXT: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY]], 0
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; SELECTED-NEXT: $q0 = COPY [[DUPv2i64lane]]
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; SELECTED-NEXT: RET_ReallyLR implicit $q0
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%1:_(<2 x s64>) = COPY $q0
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%2:_(<2 x s64>) = G_IMPLICIT_DEF
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%4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0)
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$q0 = COPY %4(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: duplane32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: duplane32
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
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; CHECK-NEXT: $q0 = COPY [[DUPLANE32_]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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;
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; SELECTED-LABEL: name: duplane32
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; SELECTED: liveins: $q0
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; SELECTED-NEXT: {{ $}}
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; SELECTED-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; SELECTED-NEXT: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY]], 0
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; SELECTED-NEXT: $q0 = COPY [[DUPv4i32lane]]
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; SELECTED-NEXT: RET_ReallyLR implicit $q0
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%1:_(<4 x s32>) = COPY $q0
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%2:_(<4 x s32>) = G_IMPLICIT_DEF
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%4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0)
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$q0 = COPY %4(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: duplane16
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: duplane16
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
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; CHECK-NEXT: $q0 = COPY [[DUPLANE16_]](<8 x s16>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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;
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; SELECTED-LABEL: name: duplane16
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; SELECTED: liveins: $q0
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; SELECTED-NEXT: {{ $}}
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; SELECTED-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; SELECTED-NEXT: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY]], 0
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; SELECTED-NEXT: $q0 = COPY [[DUPv8i16lane]]
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; SELECTED-NEXT: RET_ReallyLR implicit $q0
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%1:_(<8 x s16>) = COPY $q0
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%2:_(<8 x s16>) = G_IMPLICIT_DEF
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%4:_(<8 x s16>) = G_SHUFFLE_VECTOR %1(<8 x s16>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
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$q0 = COPY %4(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: duplane8
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: duplane8
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
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; CHECK-NEXT: $q0 = COPY [[DUPLANE8_]](<16 x s8>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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;
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; SELECTED-LABEL: name: duplane8
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; SELECTED: liveins: $q0
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; SELECTED-NEXT: {{ $}}
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; SELECTED-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; SELECTED-NEXT: [[DUPv16i8lane:%[0-9]+]]:fpr128 = DUPv16i8lane [[COPY]], 0
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; SELECTED-NEXT: $q0 = COPY [[DUPv16i8lane]]
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; SELECTED-NEXT: RET_ReallyLR implicit $q0
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%1:_(<16 x s8>) = COPY $q0
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%2:_(<16 x s8>) = G_IMPLICIT_DEF
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%4:_(<16 x s8>) = G_SHUFFLE_VECTOR %1(<16 x s8>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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$q0 = COPY %4(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32_duplane32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: v2s32_duplane32
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY1]](<2 x s32>), [[DEF]](<2 x s32>)
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; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
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; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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;
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; SELECTED-LABEL: name: v2s32_duplane32
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; SELECTED: liveins: $d0, $d1
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; SELECTED-NEXT: {{ $}}
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; SELECTED-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
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; SELECTED-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; SELECTED-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; SELECTED-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
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; SELECTED-NEXT: $d0 = COPY [[DUPv2i32lane]]
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; SELECTED-NEXT: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_IMPLICIT_DEF
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%3:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0)
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$d0 = COPY %3(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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