derek.holloway
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84 lines
2.6 KiB
YAML
84 lines
2.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: or_combine_sext
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; or (sext X), (sext Y) --> sext (or X, Y)
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; CHECK-LABEL: name: or_combine_sext
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %y:_(s32) = COPY $w1
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
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; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[OR]](s32)
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; CHECK-NEXT: $x0 = COPY %logic_op(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%x:_(s32) = COPY $w0
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%y:_(s32) = COPY $w1
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%hand1:_(s64) = G_SEXT %x(s32)
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%hand2:_(s64) = G_SEXT %y(s32)
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%logic_op:_(s64) = G_OR %hand1, %hand2
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$x0 = COPY %logic_op(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: illegal_ty
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; Post-legalization, we should not perform the optimization here, since
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; it would create an illegal G_OR.
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; CHECK-LABEL: name: illegal_ty
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x_wide:_(s32) = COPY $w0
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; CHECK-NEXT: %y_wide:_(s32) = COPY $w1
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; CHECK-NEXT: %x:_(s1) = G_TRUNC %x_wide(s32)
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; CHECK-NEXT: %y:_(s1) = G_TRUNC %y_wide(s32)
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; CHECK-NEXT: %hand1:_(s64) = G_SEXT %x(s1)
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; CHECK-NEXT: %hand2:_(s64) = G_SEXT %y(s1)
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; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2
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; CHECK-NEXT: $x0 = COPY %logic_op(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%x_wide:_(s32) = COPY $w0
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%y_wide:_(s32) = COPY $w1
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%x:_(s1) = G_TRUNC %x_wide
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%y:_(s1) = G_TRUNC %y_wide
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%hand1:_(s64) = G_SEXT %x(s1)
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%hand2:_(s64) = G_SEXT %y(s1)
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%logic_op:_(s64) = G_OR %hand1, %hand2
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$x0 = COPY %logic_op(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_combine_physreg
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tracksRegLiveness: true
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legalized: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; Post-legalization, we must not crash here.
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; CHECK-LABEL: name: dont_combine_physreg
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %x:_(s32) = COPY $w0
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; CHECK-NEXT: %y:_(s32) = COPY $w1
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; CHECK-NEXT: %logic_op:_(s32) = G_OR %x, %y
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; CHECK-NEXT: $w0 = COPY %logic_op(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%x:_(s32) = COPY $w0
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%y:_(s32) = COPY $w1
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%logic_op:_(s32) = G_OR %x, %y
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$w0 = COPY %logic_op(s32)
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RET_ReallyLR implicit $w0
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