derek.holloway
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110 lines
3.1 KiB
YAML
110 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombiner-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s
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# REQUIRES: asserts
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# Check that we simplify the constant rotate amount to be in range.
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---
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name: rotl
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; CHECK-LABEL: name: rotl
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%5:_(s64) = G_CONSTANT i64 -16
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%2:_(s32) = G_ROTL %0, %5(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; CHECK-LABEL: name: rotr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[ROTR]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%5:_(s64) = G_CONSTANT i64 -16
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%2:_(s32) = G_ROTR %0, %5(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotl_bitwidth_cst
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; CHECK-LABEL: name: rotl_bitwidth_cst
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%5:_(s64) = G_CONSTANT i64 32
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%2:_(s32) = G_ROTL %0, %5(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotl_bitwidth_minus_one_cst
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; CHECK-LABEL: name: rotl_bitwidth_minus_one_cst
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
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; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%5:_(s64) = G_CONSTANT i64 31
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%2:_(s32) = G_ROTL %0, %5(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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