derek.holloway
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89 lines
3.5 KiB
YAML
89 lines
3.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple aarch64 -passes=aarch64-post-select-optimize %s -o - | FileCheck %s
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---
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name: pluto
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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- { reg: '$x2' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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body: |
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; CHECK-LABEL: name: pluto
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w1, $x0, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[DEF]]
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 872415232
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
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; CHECK-NEXT: FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
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; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY1]], 1, 0
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWri]], %subreg.sub_32
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[DEF]]
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; CHECK-NEXT: FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
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; CHECK-NEXT: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK-NEXT: TBNZW [[EORWrr]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 60, 59
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; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[UBFMXri]], 0, 0 :: (load (s32))
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[DEF]]
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; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY6]], [[LDRSroX]], implicit $fpcr
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr32 = COPY [[DEF]]
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; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[FMULSrr]], [[COPY7]], implicit $fpcr
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; CHECK-NEXT: STRSui [[FADDSrr]], [[COPY2]], 0 :: (store (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: RET_ReallyLR
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bb.1:
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liveins: $w1, $x0, $x2
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%0:gpr64sp = COPY $x0
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%1:gpr32sp = COPY $w1
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%2:gpr64sp = COPY $x2
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%3:gpr32 = IMPLICIT_DEF
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%29:fpr32 = COPY %3
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%33:gpr32 = MOVi32imm 872415232
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%4:fpr32 = COPY %33
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FCMPSrr %29, %4, implicit-def $nzcv, implicit $fpcr
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%28:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
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%7:gpr32 = SUBSWri %1, 1, 0, implicit-def $nzcv
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%8:gpr64 = SUBREG_TO_REG %7, %subreg.sub_32
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%30:fpr32 = COPY %3
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FCMPSrr %30, %4, implicit-def $nzcv, implicit $fpcr
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%27:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
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%26:gpr32 = EORWrr %28, %27
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TBNZW %26, 0, %bb.3
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B %bb.2
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bb.2:
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%12:gpr64 = UBFMXri %8, 60, 59
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%15:fpr32 = LDRSroX %0, %12, 0, 0 :: (load (s32))
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%31:fpr32 = COPY %3
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%16:fpr32 = FMULSrr %31, %15, implicit $fpcr
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%32:fpr32 = COPY %3
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%17:fpr32 = FADDSrr %16, %32, implicit $fpcr
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STRSui %17, %2, 0 :: (store (s32))
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bb.3:
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RET_ReallyLR
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...
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