derek.holloway
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40 lines
1.2 KiB
YAML
40 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
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# Check we don't try to combine a load of < s8 as that will end up creating a illegal non-extending load.
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--- |
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define i8 @test(ptr %ptr) {
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ret i8 undef
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}
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...
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---
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name: test
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: test
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[COPY]](p0) :: (load (s1) from %ir.ptr)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s1)
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; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(s1) = G_LOAD %0(p0) :: (load (s1) from %ir.ptr)
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%2:_(s8) = G_ZEXT %1(s1)
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%3:_(s32) = G_ANYEXT %2(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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