TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify register banks for G_DUP.
#

...
---
name:            v4s32_gpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0

    ; CHECK-LABEL: name: v4s32_gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s32) = COPY $w0
    %4:_(<4 x s32>) = G_DUP %0(s32)
    $q0 = COPY %4(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            v4s64_gpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: v4s64_gpr
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s64) = COPY $x0
    %4:_(<2 x s64>) = G_DUP %0(s64)
    $q0 = COPY %4(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            v2s32_gpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0

    ; CHECK-LABEL: name: v2s32_gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
    ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:_(s32) = COPY $w0
    %4:_(<2 x s32>) = G_DUP %0(s32)
    $d0 = COPY %4(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            v4s32_fpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0

    ; CHECK-LABEL: name: v4s32_fpr
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s32) = COPY $s0
    %4:_(<4 x s32>) = G_DUP %0(s32)
    $q0 = COPY %4(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            v2s64_fpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $d0

    ; CHECK-LABEL: name: v2s64_fpr
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s64) = COPY $d0
    %4:_(<2 x s64>) = G_DUP %0(s64)
    $q0 = COPY %4(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            v2s32_fpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0

    ; CHECK-LABEL: name: v2s32_fpr
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
    ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:_(s32) = COPY $s0
    %4:_(<2 x s32>) = G_DUP %0(s32)
    $d0 = COPY %4(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            v2s64_fpr_copy
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $d0

    ; CHECK-LABEL: name: v2s64_fpr_copy
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s64) = COPY $d0
    %6:_(<2 x s64>) = G_DUP %0(s64)
    $q0 = COPY %6(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            v416s8_gpr
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0

    ; CHECK-LABEL: name: v416s8_gpr
    ; CHECK: liveins: $w0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK-NEXT: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gpr(i32) = G_ANYEXT %trunc(s8)
    ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP [[ANYEXT]](i32)
    ; CHECK-NEXT: $q0 = COPY [[DUP]](<16 x s8>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(s32) = COPY $w0
    %trunc:_(s8) = G_TRUNC %0(s32)
    %1:_(<16 x s8>) = G_DUP %trunc(s8)
    $q0 = COPY %1(<16 x s8>)
    RET_ReallyLR implicit $q0

...