TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -mattr=+fullfp16 %s -o - | FileCheck %s

# CHECK-NOT: gpr

...
---
name:            test_f16.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $h0

    ; CHECK-LABEL: name: test_f16.round
    ; CHECK: liveins: $h0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s16) = COPY $h0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s16) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $h0 = COPY [[INTRINSIC_ROUND]](s16)
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:_(s16) = COPY $h0
    %1:_(s16) = G_INTRINSIC_ROUND %0
    $h0 = COPY %1(s16)
    RET_ReallyLR implicit $h0

...
---
name:            test_f32.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $s0

    ; CHECK-LABEL: name: test_f32.round
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s32) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $s0 = COPY [[INTRINSIC_ROUND]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:_(s32) = COPY $s0
    %1:_(s32) = G_INTRINSIC_ROUND %0
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            test_f64.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_f64.round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(s64) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $d0 = COPY [[INTRINSIC_ROUND]](s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:_(s64) = COPY $d0
    %1:_(s64) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(s64)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8f16.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v8f16.round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s16>) = COPY $q0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<8 x s16>) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $q0 = COPY [[INTRINSIC_ROUND]](<8 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v4f16.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v4f16.round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s16>) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $d0 = COPY [[INTRINSIC_ROUND]](<4 x s16>)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2f32.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v2f32.round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4f32.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v4f32.round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v2f64.round
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v2f64.round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
    ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:fpr(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
    ; CHECK-NEXT: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<2 x s64>)
    RET_ReallyLR implicit $q0