TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s

define <1 x float> @ret_v1f32(<1 x float> %v) {
  ; CHECK-LABEL: name: ret_v1f32
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
  ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[UV]](f32), [[DEF]](f32)
  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<2 x f32>)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x float> %v
}

define <1 x ptr> @ret_v1p0(<1 x ptr> %v) {
  ; CHECK-LABEL: name: ret_v1p0
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $d0
  ; CHECK-NEXT:   $d0 = COPY [[COPY]](p0)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x ptr> %v
}

define <1 x ptr addrspace(1)> @ret_v1p1(<1 x ptr addrspace(1)> %v) {
  ; CHECK-LABEL: name: ret_v1p1
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p1) = COPY $d0
  ; CHECK-NEXT:   $d0 = COPY [[COPY]](p1)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x ptr addrspace(1)> %v
}

define <1 x i16> @ret_v1i16(<1 x i16> %v) {
  ; CHECK-LABEL: name: ret_v1i16
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16)
  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<4 x i16>)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x i16> %v
}

define <1 x i8> @ret_v1i8(<1 x i8> %v) {
  ; CHECK-LABEL: name: ret_v1i8
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](<8 x i8>)
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[UV]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<8 x i8>)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x i8> %v
}

define <1 x i32> @ret_v1i32(<1 x i32> %v) {
  ; CHECK-LABEL: name: ret_v1i32
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[DEF]](i32)
  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<2 x i32>)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x i32> %v
}

define <1 x i64> @ret_v1i64(<1 x i64> %v) {
  ; CHECK-LABEL: name: ret_v1i64
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i64) = COPY $d0
  ; CHECK-NEXT:   $d0 = COPY [[COPY]](i64)
  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
  ret <1 x i64> %v
}
define <1 x i1> @ret_v1i1(<1 x i1> %v) {
  ; CHECK-LABEL: name: ret_v1i1
  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(i32) = COPY $w0
  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[COPY]](i32)
  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[TRUNC]](i1)
  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
  ; CHECK-NEXT:   $w0 = COPY [[ANYEXT]](i32)
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  ret <1 x i1> %v
}