derek.holloway
7502bf64a4
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804 lines
24 KiB
YAML
804 lines
24 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: add_sext_s32_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x2
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; CHECK-LABEL: name: add_sext_s32_to_s64
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; CHECK: liveins: $w1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
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; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
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; CHECK-NEXT: $x3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $x3
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%1:gpr(i32) = COPY $w1
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%ext:gpr(i64) = G_SEXT %1(i32)
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%add_lhs:gpr(i64) = COPY $x2
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%res:gpr(i64) = G_ADD %add_lhs, %ext
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$x3 = COPY %res(i64)
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RET_ReallyLR implicit $x3
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...
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---
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name: add_and_s32_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x1, $x2
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; CHECK-LABEL: name: add_and_s32_to_s64
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; CHECK: liveins: $x1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
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; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
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; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
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; CHECK-NEXT: $x3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $x3
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%1:gpr(i64) = COPY $x1
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%mask:gpr(i64) = G_CONSTANT i64 4294967295 ; 0xffff
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%ext:gpr(i64) = G_AND %1(i64), %mask
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%add_lhs:gpr(i64) = COPY $x2
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%res:gpr(i64) = G_ADD %add_lhs, %ext
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$x3 = COPY %res(i64)
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RET_ReallyLR implicit $x3
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...
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---
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name: add_sext_s16_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_sext_s16_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(i16) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_SEXT %1(i16)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_zext_s16_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_zext_s16_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(i16) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_ZEXT %1(i16)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_anyext_s16_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_anyext_s16_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(i16) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_ANYEXT %1(i16)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_and_s16_to_s32_uxtb
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_and_s16_to_s32_uxtb
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%1:gpr(i32) = COPY $w1
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%mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
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%ext:gpr(i32) = G_AND %1(i32), %mask
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_and_s16_to_s32_uxth
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_and_s16_to_s32_uxth
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%1:gpr(i32) = COPY $w1
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%mask:gpr(i32) = G_CONSTANT i32 65535 ; 0xffff
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%ext:gpr(i32) = G_AND %1(i32), %mask
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_sext_s8_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_sext_s8_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(s8) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_SEXT %1(s8)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_zext_s8_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_zext_s8_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(s8) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_ZEXT %1(s8)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_anyext_s8_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_anyext_s8_to_s32
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(s8) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_ANYEXT %1(s8)
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_sext_with_shl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_sext_with_shl
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%wide_1:gpr(i32) = COPY $w1
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%1:gpr(i16) = G_TRUNC %wide_1
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%ext:gpr(i32) = G_SEXT %1(i16)
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%imm:gpr(i32) = G_CONSTANT i32 3
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%shl:gpr(i32) = G_SHL %ext, %imm
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %shl
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: add_and_with_shl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: add_and_with_shl
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
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; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%1:gpr(i32) = COPY $w1
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%mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
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%ext:gpr(i32) = G_AND %1(i32), %mask
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%imm:gpr(i32) = G_CONSTANT i32 3
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%shl:gpr(i32) = G_SHL %ext, %imm
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %shl
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: dont_fold_invalid_mask
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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; Check that we only fold when we have a supported AND mask.
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: dont_fold_invalid_mask
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: %mask:gpr32 = MOVi32imm 42
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; CHECK-NEXT: %ext:gpr32 = ANDWrr [[COPY]], %mask
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; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
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; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext
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; CHECK-NEXT: $w3 = COPY %res
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; CHECK-NEXT: RET_ReallyLR implicit $w3
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%1:gpr(i32) = COPY $w1
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%mask:gpr(i32) = G_CONSTANT i32 42
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%ext:gpr(i32) = G_AND %1(i32), %mask
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%add_lhs:gpr(i32) = COPY $w2
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%res:gpr(i32) = G_ADD %add_lhs, %ext
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$w3 = COPY %res(i32)
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RET_ReallyLR implicit $w3
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...
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---
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name: dont_fold_invalid_shl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $w2, $x2
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; CHECK-LABEL: name: dont_fold_invalid_shl
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; CHECK: liveins: $w1, $w2, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
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; CHECK-NEXT: %ext:gpr32 = SBFMWri %wide_1, 0, 15
|
|
; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(i16) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_SEXT %1(i16)
|
|
%imm:gpr(i32) = G_CONSTANT i32 5
|
|
%shl:gpr(i32) = G_SHL %ext, %imm
|
|
%add_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_ADD %add_lhs, %shl
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_sext_s32_to_s64
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $x2
|
|
; CHECK-LABEL: name: sub_sext_s32_to_s64
|
|
; CHECK: liveins: $w1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr64sp = COPY $x2
|
|
; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $x3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x3
|
|
%1:gpr(i32) = COPY $w1
|
|
%ext:gpr(i64) = G_SEXT %1(i32)
|
|
%sub_lhs:gpr(i64) = COPY $x2
|
|
%res:gpr(i64) = G_SUB %sub_lhs, %ext
|
|
$x3 = COPY %res(i64)
|
|
RET_ReallyLR implicit $x3
|
|
...
|
|
---
|
|
name: sub_sext_s16_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_sext_s16_to_s32
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(i16) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_SEXT %1(i16)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_zext_s16_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_zext_s16_to_s32
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(i16) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_ZEXT %1(i16)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_anyext_s16_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_anyext_s16_to_s32
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(i16) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_ANYEXT %1(i16)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_and_s16_to_s32_uxtb
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%1:gpr(i32) = COPY $w1
|
|
%mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
|
|
%ext:gpr(i32) = G_AND %1(i32), %mask
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_and_s16_to_s32_uxth
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_and_s16_to_s32_uxth
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%1:gpr(i32) = COPY $w1
|
|
%mask:gpr(i32) = G_CONSTANT i32 65535 ; 0xffff
|
|
%ext:gpr(i32) = G_AND %1(i32), %mask
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
---
|
|
name: sub_sext_s8_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(s8) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_SEXT %1(s8)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_zext_s8_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_zext_s8_to_s32
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(s8) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_ZEXT %1(s8)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_anyext_s8_to_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_anyext_s8_to_s32
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(s8) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_ANYEXT %1(s8)
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %ext
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
---
|
|
...
|
|
---
|
|
name: sub_sext_with_shl
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_sext_with_shl
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%wide_1:gpr(i32) = COPY $w1
|
|
%1:gpr(i16) = G_TRUNC %wide_1
|
|
%ext:gpr(i32) = G_SEXT %1(i16)
|
|
%imm:gpr(i32) = G_CONSTANT i32 3
|
|
%shl:gpr(i32) = G_SHL %ext, %imm
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %shl
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: sub_and_with_shl
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $w1, $w2, $x2
|
|
; CHECK-LABEL: name: sub_and_with_shl
|
|
; CHECK: liveins: $w1, $w2, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
|
|
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w3 = COPY %res
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w3
|
|
%1:gpr(i32) = COPY $w1
|
|
%mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
|
|
%ext:gpr(i32) = G_AND %1(i32), %mask
|
|
%imm:gpr(i32) = G_CONSTANT i32 3
|
|
%shl:gpr(i32) = G_SHL %ext, %imm
|
|
%sub_lhs:gpr(i32) = COPY $w2
|
|
%res:gpr(i32) = G_SUB %sub_lhs, %shl
|
|
$w3 = COPY %res(i32)
|
|
RET_ReallyLR implicit $w3
|
|
...
|
|
---
|
|
name: store_16b_zext
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$w1' }
|
|
- { reg: '$x2' }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: store_16b_zext
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
|
|
; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
|
|
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:gpr(i32) = COPY $w1
|
|
%2:gpr(p0) = COPY $x2
|
|
%small:gpr(i16) = G_TRUNC %1
|
|
%zext:gpr(i64) = G_ZEXT %small(i16)
|
|
%cst:gpr(i64) = G_CONSTANT i64 3
|
|
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
|
|
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
|
|
G_STORE %2(p0), %gep(p0) :: (store (p0))
|
|
RET_ReallyLR
|
|
...
|
|
---
|
|
name: store_8b_zext
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$w1' }
|
|
- { reg: '$x2' }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: store_8b_zext
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
|
|
; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
|
|
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:gpr(i32) = COPY $w1
|
|
%2:gpr(p0) = COPY $x2
|
|
%small:gpr(s8) = G_TRUNC %1
|
|
%zext:gpr(i64) = G_ZEXT %small(s8)
|
|
%cst:gpr(i64) = G_CONSTANT i64 3
|
|
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
|
|
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
|
|
G_STORE %2(p0), %gep(p0) :: (store (p0))
|
|
RET_ReallyLR
|
|
...
|
|
---
|
|
name: store_16b_sext
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$w1' }
|
|
- { reg: '$x2' }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: store_16b_sext
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
|
|
; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
|
|
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:gpr(i32) = COPY $w1
|
|
%2:gpr(p0) = COPY $x2
|
|
%small:gpr(i16) = G_TRUNC %1
|
|
%zext:gpr(i64) = G_SEXT %small(i16)
|
|
%cst:gpr(i64) = G_CONSTANT i64 3
|
|
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
|
|
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
|
|
G_STORE %2(p0), %gep(p0) :: (store (p0))
|
|
RET_ReallyLR
|
|
...
|
|
---
|
|
name: store_8b_sext
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$w1' }
|
|
- { reg: '$x2' }
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; CHECK-LABEL: name: store_8b_sext
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
|
|
; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
|
|
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
|
|
; CHECK-NEXT: RET_ReallyLR
|
|
%0:gpr(p0) = COPY $x0
|
|
%1:gpr(i32) = COPY $w1
|
|
%2:gpr(p0) = COPY $x2
|
|
%small:gpr(s8) = G_TRUNC %1
|
|
%zext:gpr(i64) = G_SEXT %small(s8)
|
|
%cst:gpr(i64) = G_CONSTANT i64 3
|
|
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
|
|
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
|
|
G_STORE %2(p0), %gep(p0) :: (store (p0))
|
|
RET_ReallyLR
|
|
...
|