derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
412 lines
12 KiB
YAML
412 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
|
|
|
---
|
|
name: add_shl_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
; CHECK-LABEL: name: add_shl_s64_rhs
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
|
|
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_SHL %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: add_shl_s64_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
; CHECK-LABEL: name: add_shl_s64_lhs
|
|
; CHECK: liveins: $x0, $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
|
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
|
|
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%4:gpr(i64) = COPY $x1
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_SHL %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %2, %4:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: sub_shl_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
; CHECK-LABEL: name: sub_shl_s64_rhs
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_SHL %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_SUB %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
---
|
|
name: add_lshr_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: add_lshr_s64_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
; CHECK-LABEL: name: add_lshr_s64_lhs
|
|
; CHECK: liveins: $x0, $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: %param2:gpr64 = COPY $x1
|
|
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
|
|
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%param2:gpr(i64) = COPY $x1
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %2, %param2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: sub_lshr_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
; CHECK-LABEL: name: sub_lshr_s64_rhs
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_SUB %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: add_ashr_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
; CHECK-LABEL: name: add_ashr_s64_rhs
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
|
|
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: add_ashr_s64_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1
|
|
; CHECK-LABEL: name: add_ashr_s64_lhs
|
|
; CHECK: liveins: $x0, $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: %param2:gpr64 = COPY $x1
|
|
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
|
|
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%param2:gpr(i64) = COPY $x1
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_ADD %2, %param2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: sub_ashr_s64_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
; CHECK-LABEL: name: sub_ashr_s64_rhs
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
|
|
%3:gpr(i64) = G_SUB %0, %2:gpr(i64)
|
|
$x0 = COPY %3:gpr(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
---
|
|
name: add_shl_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_SHL %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: add_shl_s32_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0, $w1
|
|
; CHECK-LABEL: name: add_shl_s32_lhs
|
|
; CHECK: liveins: $w0, $w1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: %param2:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
|
|
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%param2:gpr(i32) = COPY $w1
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_SHL %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: sub_shl_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: sub_shl_s32_rhs
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_SHL %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_SUB %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: add_lshr_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: add_lshr_s32_rhs
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
|
|
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: add_lshr_s32_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0, $w1
|
|
; CHECK-LABEL: name: add_lshr_s32_lhs
|
|
; CHECK: liveins: $w0, $w1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: %param2:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
|
|
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%param2:gpr(i32) = COPY $w1
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: sub_lshr_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: sub_lshr_s32_rhs
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_SUB %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: add_ashr_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: add_ashr_s32_rhs
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
|
|
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: add_ashr_s32_lhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0, $w1
|
|
; CHECK-LABEL: name: add_ashr_s32_lhs
|
|
; CHECK: liveins: $w0, $w1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: %param2:gpr32 = COPY $w1
|
|
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
|
|
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%param2:gpr(i32) = COPY $w1
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: sub_ashr_s32_rhs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: sub_ashr_s32_rhs
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
|
|
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
|
|
%3:gpr(i32) = G_SUB %0, %2:gpr(i32)
|
|
$w0 = COPY %3:gpr(i32)
|
|
RET_ReallyLR implicit $w0
|