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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: test
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 145185
; CHECK-NEXT: TBNZW [[MOVi32imm]], 0, %bb.2
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $w5 = COPY [[MOVi32imm]]
; CHECK-NEXT: B %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[MOVi32imm]], [[MOVi32imm]]
; CHECK-NEXT: $w3 = COPY [[ADDWrr]]
; CHECK-NEXT: B %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.4(0x40000000), %bb.3(0x40000000)
liveins: $w0, $w1
%35:gpr(i32) = G_CONSTANT i32 145185
G_BRCOND %35(i32), %bb.4
G_BR %bb.3
bb.3:
successors: %bb.5(0x80000000)
%17:gpr(i32) = G_CONSTANT_FOLD_BARRIER %35
$w5 = COPY %17(i32)
G_BR %bb.5
bb.4:
successors: %bb.5(0x80000000)
%23:gpr(i32) = G_ADD %35, %35
$w3 = COPY %23(i32)
G_BR %bb.5
bb.5:
RET_ReallyLR