derek.holloway
7502bf64a4
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337 lines
10 KiB
YAML
337 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: si64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: si64
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[COPY]], 1
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; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:fpr(<4 x s32>) = COPY $q0
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%3:gpr(s64) = G_CONSTANT i64 1
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%2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
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%5:gpr(s32) = COPY %2(s32)
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%4:gpr(s64) = G_SEXT %5(s32)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: si64_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: si64_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:fpr(<2 x s32>) = COPY $d0
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%3:gpr(s64) = G_CONSTANT i64 1
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%2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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%5:gpr(s32) = COPY %2(s32)
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%4:gpr(s64) = G_SEXT %5(s32)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: zi64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: zi64
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 1
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32
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; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:fpr(<4 x s32>) = COPY $q0
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%3:gpr(s64) = G_CONSTANT i64 1
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%2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
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%5:gpr(s32) = COPY %2(s32)
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%4:gpr(s64) = G_ZEXT %5(s32)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: zi64_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: zi64_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32
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; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:fpr(<2 x s32>) = COPY $d0
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%3:gpr(s64) = G_CONSTANT i64 1
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%2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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%5:gpr(s32) = COPY %2(s32)
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%4:gpr(s64) = G_ZEXT %5(s32)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: si32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: si32
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[COPY]], 1
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; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<8 x s16>) = COPY $q0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
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%6:gpr(s16) = COPY %3(s16)
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%5:gpr(s32) = G_SEXT %6(s16)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: zi32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: zi32
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[COPY]], 1
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; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<8 x s16>) = COPY $q0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
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%6:gpr(s16) = COPY %3(s16)
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%5:gpr(s32) = G_ZEXT %6(s16)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: si32_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: si32_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<4 x s16>) = COPY $d0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
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%6:gpr(s16) = COPY %3(s16)
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%5:gpr(s32) = G_SEXT %6(s16)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: zi32_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: zi32_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<4 x s16>) = COPY $d0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
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%6:gpr(s16) = COPY %3(s16)
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%5:gpr(s32) = G_ZEXT %6(s16)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: si16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: si16
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[COPY]], 1
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; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<16 x s8>) = COPY $q0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
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%7:gpr(s8) = COPY %3(s8)
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%6:gpr(s32) = G_SEXT %7(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: zi16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: zi16
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; CHECK: liveins: $q0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 1
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; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<16 x s8>) = COPY $q0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
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%7:gpr(s8) = COPY %3(s8)
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%6:gpr(s32) = G_ZEXT %7(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: si16_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: si16_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<8 x s8>) = COPY $d0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
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%7:gpr(s8) = COPY %3(s8)
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%6:gpr(s32) = G_SEXT %7(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: zi16_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: zi16_2
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; CHECK: liveins: $d0, $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<8 x s8>) = COPY $d0
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%4:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
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%7:gpr(s8) = COPY %3(s8)
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%6:gpr(s32) = G_ZEXT %7(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: skip_anyext_to_16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: skip_anyext_to_16
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr8 = COPY [[DEF]].bsub
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.bsub
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%5:fpr(<16 x s8>) = G_IMPLICIT_DEF
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%12:gpr(s64) = G_CONSTANT i64 0
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%4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)
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%11:gpr(s8) = COPY %4(s8)
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%8:gpr(s16) = G_ANYEXT %11(s8)
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%ext:gpr(s32) = G_ANYEXT %8(s16)
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$w0 = COPY %ext(s32)
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...
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