derek.holloway
7502bf64a4
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169 lines
5.1 KiB
YAML
169 lines
5.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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# Verify that we get FCMPSri when we compare against 0.0 and that we get
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# FCMPSrr otherwise.
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...
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---
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name: zero
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: zero
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(oeq), %0(f32), %2
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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---
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name: notzero
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: notzero
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112
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; CHECK-NEXT: nofpexcept FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 1.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(oeq), %0(f32), %2
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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---
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name: notzero_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: notzero_s64
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
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; CHECK-NEXT: nofpexcept FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f64) = COPY $d0
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%1:fpr(f64) = COPY $d1
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%2:fpr(f64) = G_FCONSTANT double 1.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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---
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name: zero_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $s0
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; CHECK-LABEL: name: zero_s64
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; CHECK: liveins: $d0, $d1, $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f64) = COPY $d0
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%1:fpr(f64) = COPY $d1
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%2:fpr(f64) = G_FCONSTANT double 0.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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---
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name: zero_lhs
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: zero_lhs
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(oeq), %2(f32), %0
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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---
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name: zero_lhs_not_commutative_pred
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $s0, $s1
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; CHECK-LABEL: name: zero_lhs_not_commutative_pred
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; CHECK: liveins: $s0, $s1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK-NEXT: nofpexcept FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
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; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(f32) = COPY $s0
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%1:fpr(f32) = COPY $s1
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%2:fpr(f32) = G_FCONSTANT float 0.000000e+00
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%3:gpr(i32) = G_FCMP floatpred(olt), %2(f32), %0
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$s0 = COPY %3(i32)
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RET_ReallyLR implicit $s0
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...
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