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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: fptrunc_s16_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: fptrunc_s16_s32_fpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
%0(f32) = COPY $s0
%1(f16) = G_FPTRUNC %0
$h0 = COPY %1(f16)
...
---
name: fptrunc_s16_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptrunc_s16_s64_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTHDr:%[0-9]+]]:fpr16 = nofpexcept FCVTHDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHDr]]
%0(f64) = COPY $d0
%1(f16) = G_FPTRUNC %0
$h0 = COPY %1(f16)
...
---
name: fptrunc_s32_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptrunc_s32_s64_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTSDr:%[0-9]+]]:fpr32 = nofpexcept FCVTSDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSDr]]
%0(f64) = COPY $d0
%1(f32) = G_FPTRUNC %0
$s0 = COPY %1(f32)
...
---
name: fptrunc_v4s16_v4s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv4i16_]]
%0(<4 x f32>) = COPY $q0
%1(<4 x f16>) = G_FPTRUNC %0
$d0 = COPY %1(<4 x f16>)
...
---
name: fptrunc_v2s32_v2s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv2i32_]]
%0(<2 x f64>) = COPY $q0
%1(<2 x f32>) = G_FPTRUNC %0
$d0 = COPY %1(<2 x f32>)
...
---
name: fpext_s32_s16_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: fpext_s32_s16_fpr
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSHr]]
%0(f16) = COPY $h0
%1(f32) = G_FPEXT %0
$s0 = COPY %1(f32)
...
---
name: fpext_s64_s16_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: fpext_s64_s16_fpr
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTDHr:%[0-9]+]]:fpr64 = nofpexcept FCVTDHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDHr]]
%0(f16) = COPY $h0
%1(f64) = G_FPEXT %0
$d0 = COPY %1(f64)
...
---
name: fpext_s64_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fpext_s64_s32_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTDSr:%[0-9]+]]:fpr64 = nofpexcept FCVTDSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDSr]]
%0(f32) = COPY $s0
%1(f64) = G_FPEXT %0
$d0 = COPY %1(f64)
...
---
name: fpext_v4s32_v4s16_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv4i16_]]
%0(<4 x f16>) = COPY $d0
%1(<4 x f32>) = G_FPEXT %0
$q0 = COPY %1(<4 x f32>)
...
---
name: fpext_v2s64_v2s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv2i32_]]
%0(<2 x f32>) = COPY $d0
%1(<2 x f64>) = G_FPEXT %0
$q0 = COPY %1(<2 x f64>)
...
---
name: sitofp_s32_s32_fpr_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: sitofp_s32_s32_fpr_gpr
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUWSri]]
%0(i32) = COPY $w0
%1(f32) = G_SITOFP %0
$s0 = COPY %1(f32)
...
---
name: sitofp_s32_s32_fpr_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept SCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFv1i32_]]
%0(i32) = COPY $s0
%1(f32) = G_SITOFP %0
$s0 = COPY %1(f32)
...
---
name: uitofp_s32_s32_fpr_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept UCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFv1i32_]]
%0(i32) = COPY $s0
%1(f32) = G_UITOFP %0
$s0 = COPY %1(f32)
...
---
name: sitofp_s32_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sitofp_s32_s64_fpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUXSri]]
%0(i64) = COPY $x0
%1(f32) = G_SITOFP %0
$s0 = COPY %1(f32)
...
---
name: sitofp_s64_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: sitofp_s64_s32_fpr
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUWDri]]
%0(i32) = COPY $w0
%1(f64) = G_SITOFP %0
$d0 = COPY %1(f64)
...
---
name: sitofp_s64_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sitofp_s64_s64_fpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUXDri]]
%0(i64) = COPY $x0
%1(f64) = G_SITOFP %0
$d0 = COPY %1(f64)
...
---
name: uitofp_s32_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: uitofp_s32_s32_fpr
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUWSri]]
%0(i32) = COPY $w0
%1(f32) = G_UITOFP %0
$s0 = COPY %1(f32)
...
---
name: uitofp_s32_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: uitofp_s32_s64_fpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUXSri]]
%0(i64) = COPY $x0
%1(f32) = G_UITOFP %0
$s0 = COPY %1(f32)
...
---
name: uitofp_s64_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: uitofp_s64_s32_fpr
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUWDri]]
%0(i32) = COPY $w0
%1(f64) = G_UITOFP %0
$d0 = COPY %1(f64)
...
---
name: uitofp_s64_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: uitofp_s64_s64_fpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUXDri]]
%0(i64) = COPY $x0
%1(f64) = G_UITOFP %0
$d0 = COPY %1(f64)
...
---
name: fptosi_s32_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: fptosi_s32_s32_gpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWSr]]
%0(f32) = COPY $s0
%1(i32) = G_FPTOSI %0
$w0 = COPY %1(i32)
...
---
name: fptosi_s32_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptosi_s32_s64_gpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWDr]]
%0(f64) = COPY $d0
%1(i32) = G_FPTOSI %0
$w0 = COPY %1(i32)
...
---
name: fptosi_s64_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: fptosi_s64_s32_gpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXSr]]
%0(f32) = COPY $s0
%1(i64) = G_FPTOSI %0
$x0 = COPY %1(i64)
...
---
name: fptosi_s64_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptosi_s64_s64_gpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXDr]]
%0(f64) = COPY $d0
%1(i64) = G_FPTOSI %0
$x0 = COPY %1(i64)
...
---
name: fptoui_s32_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: fptoui_s32_s32_gpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWSr]]
%0(f32) = COPY $s0
%1(i32) = G_FPTOUI %0
$w0 = COPY %1(i32)
...
---
name: fptoui_s32_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptoui_s32_s64_gpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWDr]]
%0(f64) = COPY $d0
%1(i32) = G_FPTOUI %0
$w0 = COPY %1(i32)
...
---
name: fptoui_s64_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: fptoui_s64_s32_gpr
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXSr]]
%0(f32) = COPY $s0
%1(i64) = G_FPTOUI %0
$x0 = COPY %1(i64)
...
---
name: fptoui_s64_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: fptoui_s64_s64_gpr
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXDr]]
%0(f64) = COPY $d0
%1(i64) = G_FPTOUI %0
$x0 = COPY %1(i64)
...
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