TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s

...
---
name:            test_f16.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $h0

    ; CHECK-LABEL: name: test_f16.rint
    ; CHECK: liveins: $h0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
    ; CHECK-NEXT: [[FRINTXHr:%[0-9]+]]:fpr16 = nofpexcept FRINTXHr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $h0 = COPY [[FRINTXHr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(f16) = COPY $h0
    %1:fpr(f16) = G_FRINT %0
    $h0 = COPY %1(f16)
    RET_ReallyLR implicit $h0

...
---
name:            test_f32.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $s0

    ; CHECK-LABEL: name: test_f32.rint
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
    ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $s0 = COPY [[FRINTXSr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:fpr(f32) = COPY $s0
    %1:fpr(f32) = G_FRINT %0
    $s0 = COPY %1(f32)
    RET_ReallyLR implicit $s0

...
---
name:            test_f64.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_f64.rint
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTXDr:%[0-9]+]]:fpr64 = nofpexcept FRINTXDr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTXDr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(f64) = COPY $d0
    %1:fpr(f64) = G_FRINT %0
    $d0 = COPY %1(f64)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4f32.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v4f32.rint
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv4f32 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTXv4f32_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<4 x f32>) = COPY $q0
    %1:fpr(<4 x f32>) = G_FRINT %0
    $q0 = COPY %1(<4 x f32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v2f64.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v2f64.rint
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv2f64 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTXv2f64_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<2 x f64>) = COPY $q0
    %1:fpr(<2 x f64>) = G_FRINT %0
    $q0 = COPY %1(<2 x f64>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v4f16.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v4f16.rint
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv4f16 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTXv4f16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<4 x f16>) = COPY $d0
    %1:fpr(<4 x f16>) = G_FRINT %0
    $d0 = COPY %1(<4 x f16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8f16.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v8f16.rint
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv8f16 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTXv8f16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<8 x f16>) = COPY $q0
    %1:fpr(<8 x f16>) = G_FRINT %0
    $q0 = COPY %1(<8 x f16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v2f32.rint
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v2f32.rint
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv2f32 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTXv2f32_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<2 x f32>) = COPY $d0
    %1:fpr(<2 x f32>) = G_FRINT %0
    $d0 = COPY %1(<2 x f32>)
    RET_ReallyLR implicit $d0

...