derek.holloway
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38 lines
1.1 KiB
YAML
38 lines
1.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @sdiv_s32_gpr() { ret void }
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...
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---
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# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
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# Also check that we constrain the register class of the COPY to GPR32.
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name: sdiv_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: sdiv_s32_gpr
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
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; CHECK-NEXT: $w0 = COPY [[SDIVWr]]
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%0(i32) = COPY $w0
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%1(i32) = COPY $w1
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%2(i32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
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$w0 = COPY %2(i32)
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...
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