TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s

...
---
name:            test_f64.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_f64.intrinsic_round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTADr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(f64) = COPY $d0
    %1:fpr(f64) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(f64)
    RET_ReallyLR implicit $d0

...
---
name:            test_f32.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $s0

    ; CHECK-LABEL: name: test_f32.intrinsic_round
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
    ; CHECK-NEXT: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $s0 = COPY [[FRINTASr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $s0
    %0:fpr(f32) = COPY $s0
    %1:fpr(f32) = G_INTRINSIC_ROUND %0
    $s0 = COPY %1(f32)
    RET_ReallyLR implicit $s0

...
---
name:            test_f16.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $h0

    ; CHECK-LABEL: name: test_f16.intrinsic_round
    ; CHECK: liveins: $h0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
    ; CHECK-NEXT: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $h0 = COPY [[FRINTAHr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $h0
    %0:fpr(f16) = COPY $h0
    %1:fpr(f16) = G_INTRINSIC_ROUND %0
    $h0 = COPY %1(f16)
    RET_ReallyLR implicit $h0

...
---
name:            test_v4f16.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v4f16.intrinsic_round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTAv4f16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<4 x f16>) = COPY $d0
    %1:fpr(<4 x f16>) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(<4 x f16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8f16.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v8f16.intrinsic_round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTAv8f16_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<8 x f16>) = COPY $q0
    %1:fpr(<8 x f16>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<8 x f16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v2f32.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v2f32.intrinsic_round
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $d0 = COPY [[FRINTAv2f32_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0
    %0:fpr(<2 x f32>) = COPY $d0
    %1:fpr(<2 x f32>) = G_INTRINSIC_ROUND %0
    $d0 = COPY %1(<2 x f32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4f32.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v4f32.intrinsic_round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTAv4f32_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<4 x f32>) = COPY $q0
    %1:fpr(<4 x f32>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<4 x f32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v2f64.intrinsic_round
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v2f64.intrinsic_round
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]], implicit $fpcr
    ; CHECK-NEXT: $q0 = COPY [[FRINTAv2f64_]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %0:fpr(<2 x f64>) = COPY $q0
    %1:fpr(<2 x f64>) = G_INTRINSIC_ROUND %0
    $q0 = COPY %1(<2 x f64>)
    RET_ReallyLR implicit $q0