derek.holloway
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70 lines
2.1 KiB
YAML
70 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: fold_ror_eor
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1.entry:
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liveins: $w0
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; Our codegen differs from SDAG here, we decide to fold in LHS
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; operand instead of RHS since they're both rotates and XOR is commutative.
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; Either is valid.
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; CHECK-LABEL: name: fold_ror_eor
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[EXTRWrri:%[0-9]+]]:gpr32 = EXTRWrri [[COPY]], [[COPY]], 11
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; CHECK-NEXT: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[EXTRWrri]], [[COPY]], 198
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; CHECK-NEXT: $w0 = COPY [[EORWrs]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i32) = COPY $w0
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%13:gpr(i64) = G_CONSTANT i64 6
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%2:gpr(i32) = G_ROTR %0, %13(i64)
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%14:gpr(i64) = G_CONSTANT i64 11
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%4:gpr(i32) = G_ROTR %0, %14(i64)
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%5:gpr(i32) = G_XOR %2, %4
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: fold_ror_eor_rhs_only
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: fold_ror_eor_rhs_only
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[COPY1]], [[COPY]], 198
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; CHECK-NEXT: $w0 = COPY [[EORWrs]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = COPY $w1
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%9:gpr(i64) = G_CONSTANT i64 6
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%3:gpr(i32) = G_ROTR %0, %9(i64)
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%4:gpr(i32) = G_XOR %1, %3
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$w0 = COPY %4(i32)
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RET_ReallyLR implicit $w0
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...
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