derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
237 lines
6.8 KiB
YAML
237 lines
6.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
|
|
---
|
|
name: shl_cimm_32
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: shl_cimm_32
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
|
|
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%1:gpr(i32) = G_CONSTANT i32 8
|
|
%2:gpr(i32) = G_SHL %0, %1(i32)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: shl_cimm_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: shl_cimm_64
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
|
|
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_SHL %0, %1(i64)
|
|
$x0 = COPY %2(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: lshr_cimm_32
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: lshr_cimm_32
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
|
|
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i32) = G_LSHR %0, %3(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: lshr_cimm_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: lshr_cimm_64
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
|
|
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_LSHR %0, %1(i64)
|
|
$x0 = COPY %2(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: ashr_cimm_32
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: ashr_cimm_32
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
|
|
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i32) = G_ASHR %0, %3(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: ashr_cimm_32_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: ashr_cimm_32_64
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32
|
|
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 -8
|
|
%2:gpr(i32) = G_ASHR %0, %3(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: lshr_cimm_32_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: lshr_cimm_32_64
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32
|
|
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 -8
|
|
%2:gpr(i32) = G_LSHR %0, %3(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: ashr_cimm_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $x0
|
|
|
|
; CHECK-LABEL: name: ashr_cimm_64
|
|
; CHECK: liveins: $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
|
|
; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%0:gpr(i64) = COPY $x0
|
|
%1:gpr(i64) = G_CONSTANT i64 8
|
|
%2:gpr(i64) = G_ASHR %0, %1(i64)
|
|
$x0 = COPY %2(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: lshr_32_notimm64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: lshr_32_notimm64
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
|
|
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
|
|
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 8
|
|
%4:gpr(i64) = G_AND %3, %3
|
|
%2:gpr(i32) = G_LSHR %0, %4(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: ashr_32_notimm64
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
liveins: $w0
|
|
|
|
; CHECK-LABEL: name: ashr_32_notimm64
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
|
|
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
|
|
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
|
%0:gpr(i32) = COPY $w0
|
|
%3:gpr(i64) = G_CONSTANT i64 8
|
|
%4:gpr(i64) = G_AND %3, %3
|
|
%2:gpr(i32) = G_ASHR %0, %4(i64)
|
|
$w0 = COPY %2(i32)
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|