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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @sextload_s32_from_s16(ptr %addr) { ret void }
define void @sextload_s32_from_s16_not_combined(ptr %addr) { ret void }
...
---
name: sextload_s32_from_s16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sextload_s32_from_s16
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (s16) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRSHWui]]
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)
$w0 = COPY %1(i32)
...
---
name: sextload_s32_from_s16_not_combined
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: sextload_s32_from_s16_not_combined
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[LDRHHui]], 0, 15
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
%0:gpr(p0) = COPY $x0
%1:gpr(i16) = G_LOAD %0 :: (load (s16) from %ir.addr)
%2:gpr(i32) = G_SEXT %1
$w0 = COPY %2(i32)
...