derek.holloway
7502bf64a4
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90 lines
3.1 KiB
LLVM
90 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
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; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 -use-constant-int-for-scalable-splat | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
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; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS
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; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 -use-constant-int-for-scalable-splat | FileCheck %s --check-prefixes=CHECK,CHECK-GS
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;; add
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define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-SDAG-LABEL: addnxv2i64:
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; CHECK-SDAG: // %bb.0: // %entry
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; CHECK-SDAG-NEXT: add z0.d, z0.d, #9 // =0x9
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; CHECK-SDAG-NEXT: ret
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;
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; CHECK-GS-LABEL: addnxv2i64:
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; CHECK-GS: // %bb.0: // %entry
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; CHECK-GS-NEXT: mov w8, #9 // =0x9
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; CHECK-GS-NEXT: mov z1.d, x8
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; CHECK-GS-NEXT: add z0.d, z0.d, z1.d
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; CHECK-GS-NEXT: ret
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entry:
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%c = add <vscale x 2 x i64> %a, splat (i64 9)
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ret <vscale x 2 x i64> %c
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}
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define <vscale x 2 x i64> @splarnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-SDAG-LABEL: splarnxv2i64:
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; CHECK-SDAG: // %bb.0: // %entry
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; CHECK-SDAG-NEXT: mov z0.d, #9 // =0x9
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; CHECK-SDAG-NEXT: ret
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;
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; CHECK-GS-LABEL: splarnxv2i64:
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; CHECK-GS: // %bb.0: // %entry
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; CHECK-GS-NEXT: mov w8, #9 // =0x9
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; CHECK-GS-NEXT: mov z0.d, x8
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; CHECK-GS-NEXT: ret
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entry:
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ret <vscale x 2 x i64> splat (i64 9)
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}
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define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-SDAG-LABEL: addnxv4i32:
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; CHECK-SDAG: // %bb.0: // %entry
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; CHECK-SDAG-NEXT: add z0.s, z0.s, #9 // =0x9
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; CHECK-SDAG-NEXT: ret
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;
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; CHECK-GS-LABEL: addnxv4i32:
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; CHECK-GS: // %bb.0: // %entry
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; CHECK-GS-NEXT: mov w8, #9 // =0x9
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; CHECK-GS-NEXT: mov z1.s, w8
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; CHECK-GS-NEXT: add z0.s, z0.s, z1.s
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; CHECK-GS-NEXT: ret
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entry:
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%c = add <vscale x 4 x i32> %a, splat (i32 9)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 4 x i32> @splatnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-SDAG-LABEL: splatnxv4i32:
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; CHECK-SDAG: // %bb.0: // %entry
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; CHECK-SDAG-NEXT: mov z0.s, #9 // =0x9
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; CHECK-SDAG-NEXT: ret
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;
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; CHECK-GS-LABEL: splatnxv4i32:
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; CHECK-GS: // %bb.0: // %entry
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; CHECK-GS-NEXT: mov w8, #9 // =0x9
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; CHECK-GS-NEXT: mov z0.s, w8
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; CHECK-GS-NEXT: ret
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entry:
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ret <vscale x 4 x i32> splat (i32 9)
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}
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define <vscale x 4 x float> @splatnxv4f32() {
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; CHECK-SDAG-LABEL: splatnxv4f32:
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; CHECK-SDAG: // %bb.0: // %entry
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; CHECK-SDAG-NEXT: fmov z0.s, #1.00000000
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; CHECK-SDAG-NEXT: ret
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;
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; CHECK-GS-LABEL: splatnxv4f32:
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; CHECK-GS: // %bb.0: // %entry
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; CHECK-GS-NEXT: fmov s0, #1.00000000
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; CHECK-GS-NEXT: fmov w8, s0
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; CHECK-GS-NEXT: mov z0.s, w8
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; CHECK-GS-NEXT: ret
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entry:
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ret <vscale x 4 x float> splat (float 1.0)
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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